D02 module would be affected by pcn 206440. TX2

Hello,
we are using jetson TX2 module with jetpack 4.2.1 and L4T 32.2.0 with our custom changes in dtsi files according to our requirement but due to mixing of shipment we have DO2 and above board.

so, we are able to flash board below DO2 (like DO ,DO1) but not DO2 so i want to change code according to patch https://developer.nvidia.com/embedded/downloads#?search=206440&tx=$product,jetson_tx2

please guide me for these changes. (Any reference for changes mention in the link)

Thanks in advance

W donā€™t have the PCN206440 overlay patch for L4T R32.2.0, but we have the one for R32.2.1, you can find it from L4T 32.2.1 | NVIDIA Developer to see if you can integrate it.

after replacing files from overlay patch i am able to successfully flash but when i reboot system it got stuck here .
any idea why ??

Logs

U-Boot 2016.07 (Jul 06 2020 - 12:48:26 +0530)

TEGRA186
Model: NVIDIA P2771-0000-500
DRAM: 7.7 GiB
MMC: Tegra SD/MMC: 0, Tegra SD/MMC: 1
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
Net: eth0: ethernet@2490000
Hit any key to stop autoboot: 0
MMC: no card present
switch to partitions #0, OK
mmc0(part 0) is current device
Scanning mmc 0:1ā€¦
starting USBā€¦
No controllers found
USB is stopped. Please issue ā€˜usb startā€™ first.
starting USBā€¦
No controllers found
ethernet@2490000 Waiting for PHY auto negotiation to completeā€¦ TIMEOUT !
ERROR: phy_startup() failed: -110
at drivers/net/dwc_eth_qos.c:894/eqos_start()
ERROR: FAILED: -110
at drivers/net/dwc_eth_qos.c:1122/eqos_start()
missing environment variable: pxeuuid
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/01-48-b0-2d-49-78-2f
ethernet@2490000 Waiting for PHY auto negotiation to completeā€¦ TIMEOUT !
ERROR: phy_startup() failed: -110
at drivers/net/dwc_eth_qos.c:894/eqos_start()
ERROR: FAILED: -110
at drivers/net/dwc_eth_qos.c:1122/eqos_start()
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/00000000
ethernet@2490000 Waiting for PHY auto negotiation to completeā€¦ TIMEOUT !
ERROR: phy_startup() failed: -110
at drivers/net/dwc_eth_qos.c:894/eqos_start()
ERROR: FAILED: -110
at drivers/net/dwc_eth_qos.c:1122/eqos_start()
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/0000000
ethernet@2490000 Waiting for PHY auto negotiation to completeā€¦ TIMEOUT !
ERROR: phy_startup() failed: -110
at drivers/net/dwc_eth_qos.c:894/eqos_start()
ERROR: FAILED: -110

Not quite sure if itā€™s re;ated with the PCN overlay patch.
Suggest to move your entire BSP to newer one.

Thanks kayccc,

how to apply overlay patch is there any document or standard methodology which I can follow.

Thanks & Regards

Hi akash.l,

Please follow below steps to apply overlay patch and flash:

$ tar xpvf Jetson_Linux_R32.1.0_aarch64.tbz2 
$ cd Linux_for_Tegra/rootfs/
$ sudo tar xpvf ../../Tegra_Linux_Sample-Root-Filesystem_R32.1.0_aarch64.tbz2 
$ cd ../../
$ tar xpvf overlay_32.2.1.tbz2 
$ cd Linux_for_Tegra/
$ sudo ./apply_binaries.sh 
$ sudo ./flash.sh jetson-tx2 mmcblk0p1
1 Like

hello carolyuu ,
Thanks for reply

I have still some issues with my custom modification of l4t.
can i get changes in dts(source file) or document what to change instead of overlay package of dtb??
I need to implement Custome modification and overlay package changes in combine for my cumtome board.

Hello,

Just in case you didnā€™t notice. The dtb file inside the overlay tarball is bpmp dtb. And we didnā€™t release the source code of bpmp dtb. Only the kernel dtb.

What is public source in the tarball is the cboot. With below patch.

diff --git a/drivers/sdmmc/tegrabl_sdmmc_protocol.h b/drivers/sdmmc/tegrabl_sdmmc_protocol.h
index 41e0718..b3fdd07 100644
--- a/drivers/sdmmc/tegrabl_sdmmc_protocol.h
+++ b/drivers/sdmmc/tegrabl_sdmmc_protocol.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * NVIDIA CORPORATION and its licensors retain all intellectual property
  * and proprietary rights in and to this software, related documentation
@@ -19,7 +19,7 @@
 #define COMMAND_TIMEOUT_IN_US					100000U
 
 /* OCR register polling timeout */
-#define OCR_POLLING_TIMEOUT_IN_US				500000U
+#define OCR_POLLING_TIMEOUT_IN_US				1000000U
 
 /* Timeout from controller side for read to be completed */
 #define READ_TIMEOUT_IN_US						200000U

Thanks,

Another question: will these PCN changes affect speed of DRAM or any other parameter? Because our product is in production, we donā€™t want to disrupt its normal operation.