Data transport question

Hello Everyone,

For my project I need to transport 14 Gpbs of raw LiDAR data from our system to a TX2. We plan to do some post processing on the GPU cores.

My first idea was to use the 12 MIPI CSI-2 lanes. I think this would work but I am worried about the trace delay requirements I found on in the carrier board specs (page 25 table 15). It states that the max delay for my cable+system is 473 ps. That is 6.7 cm of trace and cable length between the TX2 header and my FPGA. I don’t think I can make that work.

My second idea was to use PCIe. Page 17 table 9 says I have 375 ps of max delay for PCIe. (5 cm of trace). Can anyone really make that work?

I don’t have a 3rd idea. I am looking into some kind of a GMSL or FPD-link III bridge but that seems like overkill for what should essentially be data transport inside of 30 cm. I thought MIPI would work over 30 cm and PCIe would work over 50cm or greater. Am I missing something here?


Hi, I think your judgement is correct.

I would suggest the PCIE choice.
Usually MIPI can work around 20+cm, PCIE cable can be extended to 7 meter if you chose some professional one.

Current generation of GMSL or FPD-Link III may make your case complex.
Since you probably need to make multiple bridge to get 14Gbps bandwidth.

Please refer to the OEM Design guide, the max trace length in Signal Routing Requirements is a total requested value out of module to meet MIPI/PCIE specification.