Is it possible to operate the DDC_CLK and DAT lines (Nano DP1_AUX_P and N pins, SFIO0) at 1.8V? If so, is there a bit (like E_IO_HV for DD MPIOs) that needs to be cleared to enable 1.8V receive?
For other GPIOs I see options in the Pinmux spreadsheet to Enable/Disable 3.3V Tolerance, but not for these pins.
Thank you for the quick reply!
We had done some digging since my initial post, and it appears as though there is a 1_8V_SEL_3_3V bit defined in the DPAUX_HYBRID_SPARE register. This was seen in the dpaux_regs.h file (kernel/nvidia/drivers/video/tegra/dc/) that comes as part of the Linux L4T Driver package.
I take it this does not apply in this case?
They are 3.3V supplied pins. So the bit should be set to 3.3V type.
My understanding from the Tegra X1 TRM and Nano Product Design guide (snips below) was that these pins are supplied by 1.8V but are 3.3V tolerant in the Open Drain mode we would use for HDMI. Did I miss something?
Not every settings are implemented to design. Please follow the Design Guide to use 3.3v only on the pins, that are validated and can be guaranteed.
I want to point out that if the monitor or other hardware uses 3.3V for clock, then although 1.8V would not harm it, it also would not work. The GPIO availability of 1.8V or 3.3V is strictly from the level shifter which can be jumpered to provide 3.3V, or not jumpered to provide 1.8V. Does your monitor also have a jumper to select? If not, then there isn’t really any reason to even consider it (I can’t imagine a 3.3V clock being stable at 1.8V).
Ok, thank you for the help!
Thanks for the reply. The DDC clock and data signals are level translated to 5V going to the outside world (to monitor or whatever). My question was about the DDC signals between Jetson Nano and that level translator - which are (currently) wired with 1.8V pull-ups on our board. So long as Jetson could receive with 1.8V logic thresholds on the data line, it would be ok I think.
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