DDR3 routing of Tegra 4 K1


I am new to route DDR3L and High-speed board. I want to know what is trace spacing 3x units Dielectric means in this. This is Embedded design guide for K1. Table is given in this link

It means that spacing between traces shall be at least three times the distance between the trace and its reference plane (i.e. thickness of the dielectric between signal layer and its reference layer)