The Tegra K1 development board uses a T-branch topology for the DDR3 memory modules. The design guide references a DRAM Pin Multiplexing Option #14 which makes routing easier. I am doing my own design using the Tegra K1 dev board as a reference but I would like to implement a fly-by topology with the DDR3 chips. Is there any documentation or additional reference guides that demonstrate how this can be done?
No such doc as currently TK1 does not support fly-by topology on DDR routing.
Also the Tegra_K1_Memory_Charaterization package is based on T-branch which means fly-by topology will not be tested and verified well with it. So better to take T-branch not fly-by.
A related question: will NVIDIA ever provide IBIS models for TK1 or we can only rely on design guide?
We have no plans to release an IBIS model for the Jetson TK1. If you do have specific questions regarding information that might be provided by an IBIS model, please start a thread and post the questions that you have.