DDR3L : Mode Register MR0,MR1, MR2,MR3


Could anyone explain how to program[write] / read the DDR3L : Mode Register [with modes MR0,MR1, MR2,MR3].

Found “SDRAM[0].EmcMrs = 0x80000d71;” in the Hynix 792 configuration file.

How can I program other modes of Mode register?

Please help out to resolve the issue.

There are some related info in TRM, Chapter 18: Memory Controller.


Thanks for information

I have already gone through the TRM, the following is the refrence EMC_MRS_0

Command Trigger: MRS
The MRS register allows software to issue an MRS command.
BA0, BA1 are used to address MRS or EMRS registers in DRAM. Although this register can also program EMRS, use the EMRS register so that the hardware registers can shadow what is in the DRAM.

Boot requirements:
This register should be parameterized in the BCT and written by the Boot ROM during cold boot.

I did not find the any code in u-boot and kernel to read/write this register with with modes MR0,MR1, MR2,MR3

Hello, alex_16:
DDR initialization is done before u-boot and kernel as TRM mentioned.
Generally, DDR configurations in BCT are tuned and verified for the board/DDR.


Hello ChenJian,

I am okay with your statements.

But how to read back and write…If you want to modify…consider this case.

Found “SDRAM[0].EmcMrs = 0x80000d71;” in the Hynix 792 configuration file.

The above one is MR0 Value , what about “MR1, MR2,MR3” values in CFG files.

Please take a look at Tegra TK1 TRM : EMC_MRS_0



Thanks for the information,

I have gone through “ EMC_MRS_0”

I am able to read the values from the registers “MRS”,“EMRS” “EMRS2” “EMRS3” …mapped to MRO,MR1,MR2,MR3…But unable to write the values to it.

Here is code :

#define NV_PA_EMC_BASE_TEGRA124 0x7001B000

struct emc_ctlr *emc=(struct emc_ctlr *)NV_PA_EMC_BASE_TEGRA124;
for (i = 0; i < 43; i++) {
addr = (uintptr_t)emc + emc_reg_addr_string[i].emc_reg_addr;
value = readl(addr);
printf(" %#x:%s: %#x\n", addr,emc_reg_addr_string[i].str, value);

Hello, alex_16:
Would you please describe your detailed goal?
Generally, those registers can only be updated through BCT, not in running time.
You can refer to NV official document ‘Jetson TK1 Memory Characterization Tool’ @ https://developer.nvidia.com/embedded/downloads#?search=memory for details.



First of all .thanks for asking the your goal?

Goal: Each DDR3L has these registers MR0,MR1, MR2,MR3 , some of these value says the drive stregth

I want to change these values read/write.

Step 1: Written code in u-boot, to read the registers [MR0,MR1,MR2,MR3]

But unable to write the modified

Hello, alex_16:
That’s not the way how it works.
To tune EMC parameters, please refer to NV official document ‘Jetson TK1 Memory Characterization Tool’ @ https://developer.nvidia.com/embedded/downloads#?search=memory, which contains full set of tools and documents for tuning, includes trimmers (programmable delay lines) and drive length controls.