I have already gone through the TRM, the following is the refrence
15.6.2.48 EMC_MRS_0
Command Trigger: MRS
The MRS register allows software to issue an MRS command.
BA0, BA1 are used to address MRS or EMRS registers in DRAM. Although this register can also program EMRS, use the EMRS register so that the hardware registers can shadow what is in the DRAM.
Boot requirements:
This register should be parameterized in the BCT and written by the Boot ROM during cold boot.
I did not find the any code in u-boot and kernel to read/write this register with with modes MR0,MR1, MR2,MR3
Hello, alex_16:
DDR initialization is done before u-boot and kernel as TRM mentioned.
Generally, DDR configurations in BCT are tuned and verified for the board/DDR.
Hello, alex_16:
Would you please describe your detailed goal?
Generally, those registers can only be updated through BCT, not in running time.
You can refer to NV official document ‘Jetson TK1 Memory Characterization Tool’ @ Jetson Download Center | NVIDIA Developer for details.
Hello, alex_16:
That’s not the way how it works.
To tune EMC parameters, please refer to NV official document ‘Jetson TK1 Memory Characterization Tool’ @ Jetson Download Center | NVIDIA Developer, which contains full set of tools and documents for tuning, includes trimmers (programmable delay lines) and drive length controls.