# Debugging CSI on TX1

**URL:** <https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308>\
**Category:** Jetson TX2\
**Created:** [March 19, 2018, 4:03pm UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308 "2018-03-19T16:03:01Z")\
**Posts on this page:** 7\
**Page:** 1

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**Author:** ![stroblme](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@stroblme](https://forums.developer.nvidia.com/u/stroblme)\
**Post date:** [March 19, 2018, 4:03pm UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308/1 "2018-03-19T16:03:01Z")

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Hi everyone,

I’m trying to read CSI registers on the TX1 using devmem2 tool.  
My setup consists of a TX1 mounted on the CarrierBoard from Leopard Imaging.  
It’s running R28.1 and I’m able to view a camera stream using argus\_camera.

For development purposes, I want to read CSI status registers. Therefore I’ve checked the TX1 Reference Manual for CSI register address and found:

CSI 5408:0000

Now to read e.g. the CSI Input Stream A Control register, which is decleared with

Offset: 0x20e | Byte Offset: 0x838

resulting in the address 0x54080A46, I’ve executed

sudo devmem2 0x54080A46

and received

/dev/mem opened.  
Memory mapped at address 0x7f8a9a6000.  
Bus error

Same as for other registers.  
If tried this with and without running camera stream in background.

Q: Any idea how to read the value at the specific address in the CSI?

Thanks for your Help!

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**Author:** ![ShaneCCC](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/shaneccc/32/14043_2.png) [@ShaneCCC](https://forums.developer.nvidia.com/u/ShaneCCC)\
**Post date:** [March 20, 2018, 2:35am UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308/2 "2018-03-20T02:35:04Z")

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Try the 0x54080a44 of 32 bit data. You can only access the end address for the 4 times like 0, 4, 8, c

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<div class="post-metadata">

**Author:** ![stroblme](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@stroblme](https://forums.developer.nvidia.com/u/stroblme)\
**Post date:** [March 22, 2018, 1:05pm UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308/3 "2018-03-22T13:05:49Z")

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Thanks for your answer.

One further question;  
When reading the CSI Control register with  
Offset: 0x295  
Byte Offset: 0xa54  
Which results in _0x54080CE9_ and with respect to address alignment (thanks to your hint) in _0x54080CE8_.

I expect that devmem2 would return a 32 bit value. But instead I receive:

sudo devmem2 0x54080CE8

Memory mapped at address 0x7f83dde000.  
Value at address 0x54080CE8 (0x7f83ddece8): 0x0

Q1: Can you give me a hint what I’m missing here?  
Q2: Is there a more convenient way to get a detailled log/report of the CSI status?

Thanks

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<div class="post-metadata">

**Author:** ![ShaneCCC](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/shaneccc/32/14043_2.png) [@ShaneCCC](https://forums.developer.nvidia.com/u/ShaneCCC)\
**Post date:** [March 29, 2018, 8:46am UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308/4 "2018-03-29T08:46:26Z")

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1. it’s 32 bit value 0x0 means 0x00000000
2. You can check the vi driver in …/kernel/kernel-4.4/drivers/media/platform/tegra/camera/vi/

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<div class="post-metadata">

**Author:** ![stroblme](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@stroblme](https://forums.developer.nvidia.com/u/stroblme)\
**Post date:** [April 17, 2018, 2:58pm UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308/5 "2018-04-17T14:58:16Z")

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Hey ShaneCCC,  
Sorry for late response,  
the folder you’ve mentioned doesn’t contain anything but a makefile on my system. Btw it’s located in

/usr/src/linux-headers-4.4.38-tegra/drivers/media/platform/tegra/camera/vi/

Is it the wrong location?

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<div class="post-metadata">

**Author:** ![ShaneCCC](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/shaneccc/32/14043_2.png) [@ShaneCCC](https://forums.developer.nvidia.com/u/ShaneCCC)\
**Post date:** [April 18, 2018, 2:25am UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308/6 "2018-04-18T02:25:37Z")

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Did you get the kernel source follow the l4t document?

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**Author:** ![nadeemm](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/nadeemm/32/367020_2.png) [@nadeemm](https://forums.developer.nvidia.com/u/nadeemm)\
**Post date:** [October 18, 2021, 6:28pm UTC](https://forums.developer.nvidia.com/t/debugging-csi-on-tx1/59308/7 "2021-10-18T18:28:48Z")

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