DESKEW When Migrating from JP4.6 to JP5.1.2

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

I have a sensor with a serializer/deserializer with 4 lanes where the speed is 2.5G (which can handle several streams using different VCs). In JP4.6, I recall that the DESKEW mechanism was not required (implemented). However, in JP5.1.2 (also in Orin), DESKEW is required.

Currently, my behavior is a bit strange. So, my first question is: Can we disable the DESKEW mechanism (perhaps by using different firmware, as disabling it in the device tree did not work)?

When the image is stuck:
When I run argus_camera for the first time, I can see the image. However, if I exit or change a mode, it becomes stuck. If I open another sensor (both on serial_a), I can see both images, and now I can also change the modes.

If I restart the deserializer (hard reset) each time, I can see the image. My question is: When is the DESKEW required?

3

Maybe use JP5.0.2 RCE firmware this firmware looks like didn’t enable the DESKEW mechanism.

4

looking here which is the debug version of JP5.0.2 seems that deskew is supported from 5.0.2 so it does not help.
So it seems that it is impossible to disable the deskew , right ?

What about the request of DESKEW ?
technically if I configure each time the deserializer than it will work (also when changing sensro modes) though if I have several stream on that serial_a (for example) the images of the other streams will freeze untill device is configured. (for a second or so)

5

The DESKEW only do once for each CSI port.

6

This is the dmesg log (filtered for RCE) when opening the argus_camera for the 1st time

[RCE] NVCSILP clock rate = 408000000 Hz.
[RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[RCE] MIPI clock = 1249999 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[RCE] ===== NVCSI Stream Configuration =====
[RCE] stream_id: PP 0, csi_port: PORT A
[RCE] Brick: PHY 0, Mode: D-PHY
[RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[RCE] Clock information:
[RCE] MIPI clock rate: 1250.00 MHz
[RCE] T_HS settle: 0, T_CLK settle: 0
[RCE] ======================================
[RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_tclk_settle tclk_settle 75
[RCE] Deskew setup message sent for port 0 num_lane 4
[RCE] tegra_nvcsi_stream_close(vm0, stream=0, csi=0)
[RCE] tegra_nvcsi_stream_tpg_disable(vm0, stream=0, vc=0)
[RCE] tegra_nvcsi_stream_tpg_disable: channel 0 is already disabled
[RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[RCE] MIPI clock = 1249999 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[RCE] ===== NVCSI Stream Configuration =====
[RCE] stream_id: PP 0, csi_port: PORT A
[RCE] Brick: PHY 0, Mode: D-PHY
[RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[RCE] Clock information:
[RCE] MIPI clock rate: 1250.00 MHz
[RCE] T_HS settle: 0, T_CLK settle: 0
[RCE] ======================================
[RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_tclk_settle tclk_settle 75
---->[RCE] Deskew setup message sent for port 0 num_lane 4
[RCE] ISR PHY 0 CIL_A 0x88
[RCE] ISR PHY 0 CIL_B 0x88
[RCE] ISR PHY 0 CIL_A 0x1c00000
[RCE] ISR PHY 0 CIL_B 0xc00000
[RCE] deskew: num_lanes:4
[RCE] deskew: csi_port:0
[RCE] deskew: clk status_bits:0xfff8000000001fff
[RCE] deskew: pf:13
[RCE] deskew: data status_bits:0x8000000000ffffff
[RCE] deskew: pf:24
[RCE] deskew: clk status_bits:0xfffc000000000fff
[RCE] deskew: pf:12
[RCE] deskew: data status_bits:0x1ffffff
[RCE] deskew: pf:25
[RCE] deskew: clk status_bits:0xfffffe0000000007
[RCE] deskew: pf:3
[RCE] deskew: data status_bits:0x3ffffffff
[RCE] deskew: pf:34
[RCE] deskew: clk status_bits:0xffffff0000000001
[RCE] deskew: pf:1
[RCE] deskew: data status_bits:0x7ffffffff
[RCE] deskew: pf:35
[RCE] deskew: clk_trim:5
[RCE] deskew: data_trim0:10
[RCE] deskew: data_trim1:11
[RCE] deskew: data_trim2:20
[RCE] deskew: data_trim3:22

Now I have disabled the serdes (as it’s already configured) and changed the mode (which is also equivilant to close the argus_camera which runs stop_stream , and then open the argus again.)
here is the log …

[RCE] tegra_nvcsi_stream_close(vm0, stream=0, csi=0)
[RCE] tegra_nvcsi_stream_tpg_disable(vm0, stream=0, vc=0)
[RCE] tegra_nvcsi_stream_tpg_disable: channel 0 is already disabled
[RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[RCE] MIPI clock = 1249999 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[RCE] ===== NVCSI Stream Configuration =====
[RCE] stream_id: PP 0, csi_port: PORT A
[RCE] Brick: PHY 0, Mode: D-PHY
[RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[RCE] Clock information:
[RCE] MIPI clock rate: 1250.00 MHz
[RCE] T_HS settle: 0, T_CLK settle: 0
[RCE] ======================================
[RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_ths_settle ths_settle 49
[RCE] nvcsi_calc_tclk_settle tclk_settle 75
--->[RCE] Deskew setup message sent for port 0 num_lane 4

As you may see I need to re-configure the serdes , problem is the same serdes is running several streams (using different VCs virtual channels) and if I configure the deserializer each time , when opening the 2nd stream , the 1st will be stuck…

again , any way to configure the RCE to “ignore/disable” the deskew (like in JP4.6?) , or after the 1st time to stop asking for it ?
BTW when there are 2 stream , I can easily change modes etc… (as long as there is at least one stream on…when closing both , it asks for the deskew again) , can this be configured ?

7

Sorry to tell current design unable to ignore/disable the deskew.
I would suggest to reset the serdes if only one stream is on/off and mode change.

Thanks

9

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