Device tree overlay help for SPI <> CAN driver

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin Nano
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1

Hi,

I’m trying to configure a device tree overlay for the TCAN4X5X module on the Jetson Orin Nano devkit, using the Jetson-IO config-by-hardware.py tool. Upon compiling the overlay, I get the following errors:

tcan.dts:75.27-92.23: Warning (spi_bus_bridge): /fragment@2/__overlay__/spi@0: incorrect #address-cells for SPI bus
tcan.dts:75.27-92.23: Warning (spi_bus_bridge): /fragment@2/__overlay__/spi@0: incorrect #size-cells for SPI bus
/boot/tcan.dtbo: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'

When I reboot, the SPI pins aren’t configured, even though the extlinux.conf file was updated to include the file mentioned above. Any idea why I might be getting these errors? The device tree binding for this device can be found here, my dts file is included below, and I’m using L4T 35.3.1, thank you!

/dts-v1/;
/plugin/;
/ {
        jetson-header-name = "Jetson 40pin Header";
        overlay-name = "TCAN4X5X";
        compatible = "nvidia,p3768-0000+p3767-0000\0nvidia,p3768-0000+p3767-0001\0nvidia,p3768-0000+p3767-0003\0nvidia,p3768-0000+p3767-0004\0nvidia,p3768-0000+p3767-0005\0nvidia,p3509-0000+p3767-0000\0nvidia,p3509-0000+p3767-0001\0nvidia,p3509-0000+p3767-0003\0nvidia,p3509-0000+p3767-0004\0nvidia,p3509-0000+p3767-0005";

        fragment@0 {
                target = <0xffffffff>;

                __overlay__ {
                        pinctrl-names = "default";
                        pinctrl-0 = <0x01>;

                        exp-header-pinmux {
                                phandle = <0x01>;

                                hdr40-pin13 {
                                        nvidia,pins = "spi3_sck_py0";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin16 {
                                        nvidia,pins = "spi3_cs1_py4";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin18 {
                                        nvidia,pins = "spi3_cs0_py3";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin22 {
                                        nvidia,pins = "spi3_miso_py1";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin37 {
                                        nvidia,pins = "spi3_mosi_py2";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };
                        };
                };
        };

    fragment@1 {
            target-path = "/";
            __overlay__ {
                    clocks {
                            can_clock: can_clock {
                                    compatible =  "fixed-clock";
                                    #clock-cells = <0>;
                                    clock-frequency =  <16000000>;
                                    clock-accuracy = <100>;
                            };
                    };
            };
    };

fragment@2 {
            target = <&hdr40_spi3>;
            __overlay__ {
                        #address-cells = <1>;
                        #size-cells = <0>;
                    spi@0 {
                            status = "okay";
                            compatible = "ti,tcan4x5x";
                            reg = <0>;
                            spi-max-frequency = <10000000>;
                            bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
                            nvidia,enable-hw-based-cs;
                            nvidia,rx-clk-tap-delay = <0x7>;
                            clocks = <&can_clock>;
                            interrupt-parent = <&gpio>;
                            interrupts = <&gpio 141  0x1>;
                            controller-data {
                                    nvidia,cs-setup-clk-count = <0x1e>;
                                    nvidia,cs-hold-clk-count  = <0x1e>;
                                    nvidia,rx-clk-tap-delay  = <0x1f>;
                                    nvidia,tx-clk-tap-delay  = <0x0>;
                            };
                    };
            };
    };


        __symbols__ {
                jetson_io_pinmux = "/fragment@0/__overlay__/exp-header-pinmux";
        };

        __fixups__ {
                pinmux = "/fragment@0:target:0";
        };

        __local_fixups__ {

                fragment@0 {

                        __overlay__ {
                                pinctrl-0 = <0x00>;
                        };
                };
        };
};
3

Hi shah2,

Are you using the devkit or custom board for Orin Nano?
What’s your Jetpack version in use?

It seems a SPI-CAN module and we haven’t verified for this module.

You could refer to the following thread of our verification with MCP251X module.
Jetson Orin NX(JP5.1.2_R35.4.1) mcp2515 can1 can send data, can not recieve data - #10 by KevinFFF

You may request the porting guide for TCAN4X5X from your vendor and refer to the similar steps as above thread.

4

Hi KevinFFF

Thanks for taking a look, I’m using the Orin Nano devkit, JetPack 5.1.1. The TCAN4550 uses a different kernel module than the MCP2515, so the steps won’t be exactly the same, but it doesn’t seem like I’m doing anything too different.

I updated the .dts file (see below) and fixed the compile issues, but when I decompile the generated .dtbo back to a .dts file I get some additional errors. I noticed the config-by-hardware.py tool doesn’t generate the .dtb file the extlinux.conf file is looking for, but there is no error message so I’m not sure why it isn’t successful? I will try posting on the vendor forums, but it seems like the fix will probably be on the Linux/NVIDIA side.

decomp_tcan.dts: Warning (unit_address_vs_reg): /__local_fixups__/fragment@4/__overlay__/tcan4x5x@0: node has a unit name, but no reg property
decomp_tcan.dts: Warning (gpios_property): /__fixups__:gpio: property size (102) is invalid, expected multiple of 4
decomp_tcan.dts: Warning (interrupts_property): /fragment@4/__overlay__/tcan4x5x@0:interrupt-parent: Invalid phandle
decomp_tcan.dts: Warning (interrupts_property): /fragment@4/__overlay__/tcan4x5x@0: Missing interrupt-parent

/dts-v1/;
/plugin/;
/ {
        jetson-header-name = "Jetson 40pin Header";
        overlay-name = "TCAN4X5X";
        compatible = "nvidia,p3768-0000+p3767-0000\0nvidia,p3768-0000+p3767-0001\0nvidia,p3768-0000+p3767-0003\0nvidia,p3768-0000+p3767-0004\0nvidia,p3768-0000+p3767-0005\0nvidia,p3509-0000+p3767-0000\0nvidia,p3509-0000+p3767-0001\0nvidia,p3509-0000+p3767-0003\0nvidia,p3509-0000+p3767-0004\0nvidia,p3509-0000+p3767-0005";

        fragment@0 {
                target = <&spi3>;
                __overlay__ {
                        status = "okay";
                };
        };

        fragment@1 {
                target = <&spidev3>;
                __overlay__ {
                        status = "disabled";
                };
        };

        fragment@2 {
                target = <&pinmux>;

                __overlay__ {
                        pinctrl-names = "default";
                        pinctrl-0 = <&hdr40_pinmux>;

                        hdr40_pinmux: header-40pin-pinmux {
                                hdr40-pin13 {
                                        nvidia,pins = "spi3_sck_py0";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin16 {
                                        nvidia,pins = "spi3_cs1_py4";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin18 {
                                        nvidia,pins = "spi3_cs0_py3";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin22 {
                                        nvidia,pins = "spi3_miso_py1";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };

                                hdr40-pin37 {
                                        nvidia,pins = "spi3_mosi_py2";
                                        nvidia,function = "spi3";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };
                        };
                        tcan4x5x_pins: tcan4x5x_pins {
                                hdr40-pin36 {
                                        nvidia,pins = "uart1_cts_pr5";
                                        nvidia,function = "rsvd1";
                                        nvidia,tristate = <0x00>;
                                        nvidia,enable-input = <0x01>;
                                };
                        };
                };
        };



        fragment@4 {
                target-path = "/";
                __overlay__ {
                        clocks {
                                can_clock: can_clock {
                                        compatible =  "fixed-clock";
                                        #clock-cells = <0>;
                                        clock-frequency =  <40000000>;
                                        clock-accuracy = <100>;
                                };
                        };
                };
        };

        fragment@5 {
                target = <&spi3>;
                __overlay__ {
                            #address-cells = <1>;
                            #size-cells = <0>;
                            tcan4x5x: tcan4x5x@0 {
                                    compatible = "ti,tcan4x5x";
                                    reg = <0>;
                                    spi-max-frequency = <10000000>;
                                    bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
                                    nvidia,enable-hw-based-cs;
                                    nvidia,rx-clk-tap-delay = <0x7>;
                                    clocks = <&can_clock>;
                                    pinctrl-names = "default";
                                    pinctrl-0 = <&tcan4x5x_pins>;
                                    interrupt-parent = <&gpio>;
                                    interrupts = <&gpio 141  0x2>;
                                    controller-data {
                                        nvidia,cs-setup-clk-count = <0x1e>;
                                        nvidia,cs-hold-clk-count  = <0x1e>;
                                        nvidia,rx-clk-tap-delay  = <0x1f>;
                                        nvidia,tx-clk-tap-delay  = <0x0>;
                            };
                    };
            };
    };
};
5

phandle is generated during compile.

You may refer to the following instruction to sync and build kernel image/dtb instead of just decompile and assemble it back to dtb.
Kernel Customization — Jetson Linux Developer Guide documentation (nvidia.com)
(you may also need to enable the kernel config for tcan4x5x)

7

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