Device tree updation

hello aravind.m90,

please refer to post #25 for setting up your build environment variables.
thanks

Hi,

Problem 1. Can you provide what will be the path in in the first command.

Problem 2. Also While running the command to create sd card image using customized kernel, its showing jetson-disk-image-creator.sh file/directory not found. I am using below mentioned command:
./jetson-disk-image-creator.sh -o kernal_image.img -b jetson-xavier-nx-devkit
(I am using Jetson Xavier NX)

Error:

bash: ./jetson-disk-image-creator.sh: No such file or directory

How i will get that .sh script. Any solution?

Thanks in Advance.

Hi aravind.m90,

Q1: Please use the same pipeline in #25 post.
$ make ARCH=arm64 O=$TEGRA_KERNEL_OUT tegra_defconfig

Q2: Tool path: /Linux_for_Tegra/tools/jetson-disk-image-creator.sh

Hi,

I didn’t found the jetson-disk-image-creator.sh script in the mentioned location. Is that because of my kernel building. I was following the same kernel customization procedure in NVIDIA website.

Thanks

hello aravind.m90,

this script file, jetson-disk-image-creator.sh, is installed with JetPack release image.
you may download NVIDIA SDK Manager to install JetPack release. after that, it’ll save the release image to your local host.
the default path as following, i.e. ~/nvidia/nvidia_sdk/JetPack_4.4_Linux_JETSON_AGX_XAVIER/Linux_for_Tegra
you should find the script file under tools folder, ./tools/jetson-disk-image-creator.sh
thanks

Hi,
Thank you. I found the script. Now i can able to flash. But as i said earlier i have to edit the device tree and enable Pllaon because i want to make CAN to work in 40 Mhz speed . I am following the procedure provided in the developer guide.

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html#wwpID0E06B0HA

But i have a doubt in editing of clocks-init section. I mentioned the part below:

  1. Edit the kernel DTS file to make CAN use PLLAON as parent and remove PLLAON from list of clocks to be disabled:
    clocks-init{
    compatible = “nvidia,clocks-config”;
    disable {
    /* Edit clocks property to remove clock provider + clock id pair for PLLAON. */
    };
    };

Here what we need to put inside disable part. Thank you.

Regards,
Aravind.

hello aravind.m90,

so you’ll need to edit the dts file to have customization,
for example, you may disassembler the dtb file into dts file,
$ dtc -I dtb -O dts -o temp.dts tegra.dtb

after that, you may convert it into a new dtb file for updating the board.
$ dtc -I dts -O dtb -o output.dtb temp.dts

Hello jerry,
Yes that i already did. I need to change the frequency of CAN to 40 MHz, For that i am trying to enable the pllaon in the device tree. i Converted the dtb file but now i need to make the edit. I was following the procedure specified in the developer guide. The link i am sharing with this message.

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html#wwpID0E06B0HA

In this link under the pllaon as clock source (5th step) i have a doubt.

  1. Edit the kernel DTS file to make CAN use PLLAON as parent and remove PLLAON from list of clocks to be disabled:

clocks-init{
compatible = “nvidia,clocks-config”;
disable {
/* Edit clocks property to remove clock provider + clock id pair for PLLAON. */
};
};

Here what we need to put inside disable part. Thank you.

Regards

remove PLLAON from list of clocks to be disabled

Hi,
PLLAON id is 94/0x5e. You mean to delete the id from the list. But That id is not present in the list.

hello aravind.m90,

you may change BPMP device tree, modify kernel and also kernel device tree.
for your reference, please check below for the steps.


Step-1. Change BPMP device tree

  1. Unpack dtb file
    cd $TOP/Linux_for_Tegra/bootloader/t186ref
    $ dtc -I dtb -O dts tegra194-a02-bpmp-p3668-a00.dtb > tegra194-a02-bpmp-p3668-a00.dts

  2. Modify CAN clock,

         clock@can1 {
             allow_fractional_divider = <0x1>;
        -    allowed-parents = <0x121 0x5b 0x13a>;
        +    allowed-parents = <0x121 0x5b 0x13a 0x5e>;
             clk-id = <0x9>;
         };
  1. Repack dtb file
    $ dtc -I dts -O dtb tegra194-a02-bpmp-p3668-a00.dts > tegra194-a02-bpmp-p3668-a00.dtb

  2. Re-flash bpmp-fw-dtb partition
    $ sudo ./flash.sh -k bpmp-fw-dtb jetson-xavier-nx-devkit mmcblk0p1

Step-2. Modify kernel and kernel device tree.

diff --git a/hardware/nvidia/platform/t19x/jakku/kernel-dts/tegra194-p3668-all-p3509-0000.dts b/hardware/nvidia/platform/t19x/jakku/kernel-dts/tegra194-p3668-all-p3509-0000.dts
index b724f6279..707b5b1d3 100644
--- a/hardware/nvidia/platform/t19x/jakku/kernel-dts/tegra194-p3668-all-p3509-0000.dts
+++ b/hardware/nvidia/platform/t19x/jakku/kernel-dts/tegra194-p3668-all-p3509-0000.dts
@@ -22,4 +22,17 @@
        nvidia,dtbbuildtime = __DATE__, __TIME__;
 
        compatible = "nvidia,p3449-0000+p3668-0000", "nvidia,p3449-0000+p3668-0001", "nvidia,p3509-0000+p3668-0000", "nvidia,p3509-0000+p3668-0001", "nvidia,tegra194";
+
+       clocks-init {
+               /delete-node/ disable;
+       };
+
+       mttcan@c310000 {
+               pll_source = "pllaon";
+               clock-names = "can_core", "can_host", "can", "pllaon";
+               clocks = <&bpmp_clks TEGRA194_CLK_CAN1_CORE>,
+                                       <&bpmp_clks TEGRA194_CLK_CAN1_HOST>,
+                                       <&bpmp_clks TEGRA194_CLK_CAN1>,
+                                       <&bpmp_clks TEGRA194_CLK_PLLAON>;
+       };
 };
diff --git a/kernel/kernel-4.9/arch/arm64/configs/tegra_defconfig b/kernel/kernel-4.9/arch/arm64/configs/tegra_defconfig
index 0fa3a1c86..9fe665e7d 100644
--- a/kernel/kernel-4.9/arch/arm64/configs/tegra_defconfig
+++ b/kernel/kernel-4.9/arch/arm64/configs/tegra_defconfig
@@ -227,8 +227,10 @@ CONFIG_DNS_RESOLVER=y
 CONFIG_NET_L3_MASTER_DEV=y
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_BPF_JIT=y
-CONFIG_CAN=m
+CONFIG_CAN=y
 CONFIG_CAN_VCAN=m
+CONFIG_CAN_RAW=y
+CONFIG_CAN_DEV=y
 CONFIG_CAN_SLCAN=m
 CONFIG_CAN_C_CAN=m
 CONFIG_CAN_CC770=m
@@ -249,7 +251,7 @@ CONFIG_CAN_GS_USB=m
 CONFIG_CAN_KVASER_USB=m
 CONFIG_CAN_PEAK_USB=m
 CONFIG_CAN_8DEV_USB=m
-CONFIG_MTTCAN=m
+CONFIG_MTTCAN=y
 CONFIG_IRDA=m
 CONFIG_BT=y
 CONFIG_BT_RFCOMM=y

Step-3. there are several ways to trigger a auto boot up task. here’s one for your reference.

  1. $ sudo touch /etc/rc.local; sudo chmod +x /etc/rc.local
  2. Edit rc.local file as follow.
#!/bin/bash -e

ifconfig can0 down
ip link set can0 up type can bitrate 1000000

exit 0

you may also refer to external wiki page to describes how to enable and verify CAN in Linux on Jetson AGX Xavier.
for example, Jetson/AGX Xavier CAN - eLinux.org
thanks

Hi jerry,

In the above method BPMP device tree i succefully updated but when i try to repack the modified kernel device tree its showing syntax error. Thank you.

Command: dtc -I dts -O dtb tegra194-p2888-0001-p2822-0000.dts > tegra194-p2888-0001-p2822-0000.dtb
Error: tegra194-p2888-0001-p2822-0000.dts:5297.29-30 syntax error
FATAL ERROR: Unable to parse input tree

Regards

hello aravind.m90,

it may caused by the node is used without definition,
there’s line number to indicate the error, please review your device tree property definitions.
thanks

Hi,
Below given is the line which i got error.

clocks = <&bpmp_clks TEGRA194_CLK_CAN1_CORE>,
<&bpmp_clks TEGRA194_CLK_CAN1_HOST>,
<&bpmp_clks TEGRA194_CLK_CAN1>,
<&bpmp_clks TEGRA194_CLK_PLLAON>;

I wrote exactly what you provide. That line i am getting error. I replaced “clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5b>;” with above mentioned clocks.

Regards

hello aravind.m90,

this is what NX’s default device tree looks like,
for example,

202 	mttcan@c310000 {
203 		status = "okay";
204 		pll_source = "pllc";
205 		clocks = <&bpmp_clks TEGRA194_CLK_CAN1_CORE>,
206 			<&bpmp_clks TEGRA194_CLK_CAN1_HOST>,
207 			<&bpmp_clks TEGRA194_CLK_CAN1>,
208 			<&bpmp_clks TEGRA194_CLK_PLLC>;
209 		clock-names = "can_core", "can_host","can", "pllc";
210 	}; 

since there’s change for the clock source, please look into your device tree for investigation,
thanks

Hi,

In the mttcan0 section i made the following edit. But when i try to convert it back to dtb its showing below given error.

edit:

pll_source = “pllaon”;
clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5b>,<&bpmp_clks, TEGRA194_CLK_PLLAON>;
clock-names = “can_core”, “can_host”, “can”, “pllaon”;

error:
dtc -I dts -O dtb tegra194-p2888-0001-p2822-0000.dts > tegra194-p2888-0001-p2822-0000.dtb
Error: tegra194-p2888-0001-p2822-0000.dts:5297.66-67 syntax error
FATAL ERROR: Unable to parse input tree

Line which shows the error is ,

clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5b>,<&bpmp_clks, TEGRA194_CLK_PLLAON>;

Thank you

hello aravind.m90,

please have a try to use AON clocks,
for exampel, <&aon_clks TEGRA194_CLK_PLLAON>
thanks

Hi Jerry,

Is it possible to edit the kernel dtb and BPMP dtb directly in jetson xavier nx board(target hardware) without help of a local host machine running ubuntu os. Thank you.

hello aravind.m90,

I’ve never tried this before, you’ll need dtc binary to disassembler the dtb file into text file for edit.
please check my previous post #41 as see-also.
thanks