Did anybody get SPI interface working on TX1?

Spidev device is ok, but now I have some questions about CS-Pin’s and more SPI devices…

  1. I have 3 devices on SPI, on SPI0 one device, and on SPI1 2 devices.

  2. Didn’t get the device on SPI0 “talking” we me… !!! Now I want double check my configuration.

  3. As “base” dts-file, I’m currently using the “tegra210-jetson-tx1-p2597-2180-a01-devkit.dts” file.

  4. Changes I did…

  5. By the way, If I’m looking into the spreadsheet, There is the SPI0 = SPI4 and this is the “Touch-SPI”.
    Did I need to remove the relevant touch settings, or is it enough to disable…

  6. Would be great, If some one can check it.

gpio@6000d000
gpio_default: default {
gpio-to-sfio = <16 17 18 19 20>;
};

This is my section for SPI0

spi@7000d400 {
		compatible = "nvidia,tegra210-spi";
		reg = <0x0 0x7000d400 0x0 0x200>;
		interrupts = <0x0 0x3b 0x4>;
		nvidia,dma-request-selector = <0x5c 0xf>;
		iommus = <0x57 0xe>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		dmas = <0x5c 0xf 0x5c 0xf>;
		dma-names = "rx", "tx";
		nvidia,clk-parents = "pll_p", "clk_m";
		status = "okay";

		prod-settings {

			prod {
				prod = <0x4 0xfffff000 0x0>;
			};

			prod_c_flash {
				status = "disabled";
				prod = <0x4 0xffffffc0 0x7>;
			};

			prod_c_loop {
				status = "disabled";
				prod = <0x4 0xfffff000 0x44b>;
			};
		};
	    spi0_0 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "spidev";
		reg = <0x0>;
		spi-max-frequency = <20000000>;
		nvidia,enable-hw-based-cs;
		nvidia,cs-setup-clk-count = <0x1e>;
		nvidia,cs-hold-clk-count = <0x1e>;
		nvidia,rx-clk-tap-delay = <0x1f>;
		nvidia,tx-clk-tap-delay = <0x0>;
	    };
	};

Here section for SPI1, on SPI1, I need to define the CS, from GPIO 19/20 for what is PIN 16/17/18 related ?

spi@7000d600 {
		compatible = "nvidia,tegra210-spi";
		reg = <0x0 0x7000d600 0x0 0x200>;
		interrupts = <0x0 0x52 0x4>;
		nvidia,dma-request-selector = <0x5c 0x10>;
		iommus = <0x57 0xe>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		dmas = <0x5c 0x10 0x5c 0x10>;
		dma-names = "rx", "tx";
		nvidia,clk-parents = "pll_p", "clk_m";
		status = "okay";

		prod-settings {
			#prod-cells = <0x3>;

			prod {
				prod = <0x4 0x0 0x16>;
			};

			prod_c_flash {
				status = "disabled";
				prod = <0x4 0xffffffc0 0x6>;
			};

			prod_c_loop {
				status = "disabled";
				prod = <0x4 0xfffff000 0x44b>;
			};
		};
	    spi1_0 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "spidev";
		status = "okay";
		reg = <0x0>;
		spi-max-frequency = <20000000>;
		nvidia,cs-setup-clk-count = <0x1e>;
		nvidia,cs-hold-clk-count = <0x1e>;
		nvidia,rx-clk-tap-delay = <0x1f>;
		nvidia,tx-clk-tap-delay = <0x0>;
		nvidia,chipselect-gpio = <&gpio_default 19 0>;
	    };
	    spi1_1 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "spidev";
		status = "okay";
		reg = <0x0>;
		spi-max-frequency = <20000000>;
		nvidia,cs-setup-clk-count = <0x1e>;
		nvidia,cs-hold-clk-count = <0x1e>;
		nvidia,rx-clk-tap-delay = <0x1f>;
		nvidia,tx-clk-tap-delay = <0x0>;
		nvidia,chipselect-gpio = <&gpio_default 20 0>;
	    };

	};

I put these entries in tegra210-jetson-cv-base-p2597-2180-a00.dts, recompiled the device tree, and copied it to the /boot folder on the TX1 (instructions are in nvidia’s L4T guide). A better way is to create your own dts and include/override the provided ones, though that’s more involved.

It is also necessary to compile the spidev driver into the kernel as described at neurorobotictech.com

spidev0.0 does not work - CS0 gets stuck
We are trying to get the SPI interfaces of our J100 and J120 carrier boards up and running. We had quite some success, but one problem we cannot resolve. This table show the 5 SPI devices on the Jetson TX1:
[url]http://www.auvidea.eu/images/auvidea/products/tx1/J120_SPI.png[/url]

The IMU (MPU-9250) on SPI0 (spidev3.0) is working fine. The CAN controller (MCP2515) on spivdev0.1 is also ok. But the spidev0.0 causes headaches. CS0 behaves very strange. On the first access it goes from 3.3V to 0V and then back up to 0.5V. There it stays. On subsequent accesses it toggles between 0.5V and 0V. It looks like that there is some kind of conflict. But this must be internal to the Jetson TX1 module. (We have 3.3V because we have level shifted the SPI1 bus of the Jetson TX1.)

I suspect that something is not configured right in the dtb file. We have reverse compiled it into the dts format. This dts file can be downloaded from:
[url]http://www.auvidea.eu/images/auvidea/products/tx1/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts.zip[/url]

I like to send sandman a big thank you for all his time and effort, to help us getting the SPI busses on the J100 and J120 to work.

Here is a complete documentation of the J120:
[url]http://auvidea.eu/download/manual/J120_technical_reference.pdf[/url]

Regards, Jurgen

dts present here (http://www.auvidea.eu/images/auvidea/products/tx1/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts.zip)looks bad in terms of chip select, nvidia,chipselect-gpio. The value has to be 0x13 and 0x14. While you have used 0x10 and 0x11. Also, you have used wrong value for cs in spi@7000d400 which is spi0

Just recheck the value using below command in target

xxd /proc/device-tree/spi@[TAB]

spi@7000d600 {
compatible = “nvidia,tegra210-spi”;
reg = <0x0 0x7000d600 0x0 0x200>;
interrupts = <0x0 0x52 0x4>;
nvidia,dma-request-selector = <0x5c 0x10>;
iommus = <0x57 0xe>;
#address-cells = <0x1>;
#size-cells = <0x0>;
dmas = <0x5c 0x10 0x5c 0x10>;
dma-names = “rx”, “tx”;
nvidia,clk-parents = “pll_p”, “clk_m”;
status = “okay”;
spi-max-frequency = <0x17d7840>;

	prod-settings {
		#prod-cells = <0x3>;

		prod {
			prod = <0x4 0x0 0x16>;
		};

		prod_c_flash {
			status = "disabled";
			prod = <0x4 0xffffffc0 0x6>;
		};

		prod_c_loop {
			status = "disabled";
			prod = <0x4 0xfffff000 0x44b>;
		};
	};

	spi1_0 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "linux,spidev", "spidev";
		reg = <0x0>;
		spi-max-frequency = <0x989680>;
		nvidia,enable-hw-based-cs;
		nvidia,cs-setup-clk-count = <0x1e>;
		nvidia,cs-hold-clk-count = <0x1e>;
		nvidia,rx-clk-tap-delay = <0x1f>;
		nvidia,tx-clk-tap-delay = <0x0>;
		nvidia,chipselect-gpio = <0x5e 0x10 0x0>;
	};

	spi1_1 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "linux,spidev", "spidev";
		reg = <0x1>;
		spi-max-frequency = <0x989680>;
		nvidia,enable-hw-based-cs;
		nvidia,cs-setup-clk-count = <0x1e>;
		nvidia,cs-hold-clk-count = <0x1e>;
		nvidia,rx-clk-tap-delay = <0x1f>;
		 = <0x0>;
		nvidia,chipselect-gpio = <0x5e 0x11 0x0>;
	};

You should follow the config posted by sandmen
};

Has anybody been able to get this to fully work? I’ve managed to compile the kernel with SPI, edit the device tree file and install it, and I get /dev/spi0.0 to show up. I connected MOSI and MISO and tried running a simple test on it but it didn’t work, not sure how to debug this now.

Hi Daniel

For SPI, please check

  1. the supply voltage of SP1 is 1.8V
  2. Routing should follow OEM Product Design Guide, Chapter 11.2.

Hi, we got this to work on our J100 and J120 carrier boards for the TX1. We connect the 9 axis MPU-9250 via SPI. This works perfect. We connect the 2 CAN controllers via SPI. And the third SPI bus is available on an external connector (J120). The level conversion from 1.8V to 3.3V is performed on the J120. So 3.3V peripherals can directly be connected.

We have compiled the kernel, the driver and modified the device tree, so that all this works out of the box. Toady we support 23.2.

There is just one issue: We have a problem with one SPI CS line which we route to our CAN controller 1. With the first access of this SPI channel this CS line become active and stays active until the next reset. This then blocks the second SPI channel and CAN controller 2. As a short term fix, we have removed the CAN controller 1 on the J120 rev 3. So that the other SPI channel cannot cause any damage. We believe that this is caused by the TX1 and possibly its configuration.

An alternative fix could be to turn this SPI CS line into a GPIO and then set it to High. This in theory should also circumvent this problem.

The J100 and J120 are documented in detail in the technical reference manuals, which can be downloaded from the Auvidea support page.
[url]http://www.auvidea.eu/index.php/support[/url]

Also the compiled kernel and support package can be downloaded from there. Please let me know, if you find any issues.

I’ve been playing around with the SPI on the TX1 and I found that the spi-tegra114 driver requires the device tree to have the nvidia,* properties to be inside a controller-data node. Otherwise a child node 'controller-data' not found error is thrown.

So the follow structure of the spi node for the device tree works and allows me to change properties like cs-hold-clk-count

spi@7000d400 {
		compatible = "nvidia,tegra210-spi";
		reg = <0x0 0x7000d400 0x0 0x200>;
		interrupts = <0x0 0x3b 0x4>;
		nvidia,dma-request-selector = <0x5c 0xf>;
		iommus = <0x57 0xe>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		dmas = <0x5c 0xf 0x5c 0xf>;
		dma-names = "rx", "tx";
		nvidia,clk-parents = "pll_p", "clk_m";
		status = "okay";

		prod-settings {

			prod {
				prod = <0x4 0xfffff000 0x0>;
			};

			prod_c_flash {
				status = "disabled";
				prod = <0x4 0xffffffc0 0x7>;
			};

			prod_c_loop {
				status = "disabled";
				prod = <0x4 0xfffff000 0x44b>;
			};
		};

	    spi0_0 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "spidev";
		reg = <0x0>;
		spi-max-frequency = <0x17d7840>;
		controller-data {
	          nvidia,enable-hw-based-cs;
	          nvidia,cs-inactive-cycles = <0x1>;
                  nvidia,cs-setup-clk-count = <0x0>;
	          nvidia,cs-hold-clk-count = <0x0>;
	          nvidia,rx-clk-tap-delay = <0x0>;
	          nvidia,tx-clk-tap-delay = <0x0>;
	      };
	    };
	};

@Auvidea

Re: “We connect the 2 CAN controllers via SPI”

Did you use MCP2515 for SPI CAN?

Default SPI stack has big rx latency which sometimes causing overflows. Did you modify it to get CAN working without RX overflows?

Did anyone get this working on 24.2? We are trying to connect a MCP2515 to SPI0 but so far we were unsuccessful. What we tried:

  1. Adjust the dts file in different ways
  2. Compiling and installing a custom kernel with CONFIG_SPI_SPIDEV and CONFIG_CAN enabled

Using the TX1 card with the DEVKIT I have problems with the J21 conector to get the proper voltage for each of the output in the SPI ‘port’ connected to a MCP2521 module.

I use the configuration from sandmen but i can only get a single device from spiX.0 so i think i was not able to use the CSX value nor the spidevX.1

I just add the gpio section and the spi0_0, interface i think i missing something.

I did the compilation from the /l4t/l4t-r24.2 branch to generate the 3.10.96-tegra module, the spi/spidev.ko, witch version are you using for the kernel an modules that works from now? maybe this version cause that i can only use a single chipselect (spidev1.1 is not loading after edit the dts/dtb files)

What is the trick to get /dev/spi driver to appear?
Do I have to rebuild the kernel? (I’m new to Linux)
I’m looking at the l4t docs “Building the NVIDIA Kernel”

and it says to use:
$ make O=$TEGRA_KERNEL_OUT tegra21_defconfig

but the closest config file name I see I see is
tegra12_defconfig
or
tegra_defconfig

The driver package I downloaded is:
https://developer.nvidia.com/embedded/dlc/l4t-jetson-tx1-driver-package-28-1

The kernel source from:
https://developer.nvidia.com/embedded/dlc/l4t-sources-28-1
errors when extracting. Does anyone else have this problem?

The tegra21_defconfig is locate the kernel/kernel-4.4/arch/arm64/configs/ not kernel/kernel-4.4/arch/arm/configs

Below is useful for SPI on TX1
https://elinux.org/Jetson/TX1_SPI

Thanks Shane. That link is very useful.
What are the correct settings for the second SPI chip select?

spi0_1 {

reg = <0x1>;

}
Do I need to add this:
nvidia,chipselect-gpio = <&gpio_default 20 0>;

I assume the 20 is a GPIO pin. Where is this number derived?

The CS0/CS1 is GPIO PC_03/PC04, you don’t need this if you only connect one device only need keep the device CS low.

I will be using both chip selects.

Do you have both chip selects working?
If so, could you post your spi@7000d400 dts entry?