Direct access to GPC-DMA registers

How do you address the Oring AGX (64GB) GPC-DMA registers?

Reading 0x02610000 (channel 0 CSR) faults, resulting in system reboot,
and reading the address returned from ioremap() gives 0xffffffff
which is not the Reset value for that register.

(Do I need mmap or something? I actually have spent much time trying to figure this out myself)

We don’t access the registers directly. Please share your use-case and why you need to access the registers. So that we can suggest next.

We’re developing a platform that has no pre-determined performance requirement.
The faster it works, the greater the application space, so I must
master each relevant subsystem.
The Orin AGX TRM documents dma register usage and I would think that
it would be best for me, i.e. most versitile and hightest performance,
to program the hardware directly. No?

Thanks for your help.

The capability of each Jetson platform is stated in module data sheet. Please use standard Jetpack release to get the throughput. It may not be stable to run the system in higher throughput.

Thank you.
Does “may not” mean that it is unknown?
Or does it mean exceeding the published throughput values is known to be unreliable or unsafe at the hardware level?
Or does it mean that it depends on other factors such as use-case, which may not be an issue in a very simple deterministic application?

You are right it is unknown. The capability in module data sheet is covered in SQA tests, so it is promising and reliable. Overclocking the system is not tested and may not be stable.

I am not considering overclocking at all.

I thought it would be best to manipulate DMA registers as documented in the TRM, without overclocking.

Is that for any reason not approved by NVIDIA?

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