Please apply below patch to tegra194-a02-bpmp-p2888-a04.dtb
clock@vic {
allowed-parents = <0xcf 0xe>;
clk-id = <0xa7>;
};
[b]+clock@plle {
+ clk-id = <0x64>;
+ pll_freq_table = <0x249f000 0x5f5e100 0x2 0x7d 0x18 0xffffffff 0xffffffff 0xffffffff 0xffffffff>;
+};[/b]
init {
fuse = <0x28 0x0 0x0 0x20000>;
};
Here is guidance for conversion.