Yes, page table programming which sets coherency attribute would be sufficient to assure coherency across cpu and device.
That’s why no explicit dma cache sync APIs are required if you use above coherent flavor of allocation and mapping.
You check the pagetable dt attribute between intel and arm, you should be able to figure out which are bits set in pagetable.
Moreover in your device dt entry you must be setting “dma-coherent” property to tell that device is capable of doing coherent dma operation.