Hello,
We are building a custom board that has a ZYNQ ultrascale FPGA and jetson SOM, In NVIDIA Jetson AGX Orin Series Data sheet, it shown in a figure that it can support various mipi lanes configurations, we want to use 1 clock and 4 data lanes in D-PHY mode, moreover our FPGA supports 1 clock and 4 data lanes config only. So,
Does the NVIDIA Jetson Orin 64G AGX support MIPI at 1 Clock and 4 Data Lane Configuration?
If it does support it, exactly what pins can be used for clock and data?
in d-phy mode, does it require only 1 clock for 4 data lanes?
Can the nvidia som take single ended mipi inputs?
if it does which pins can be used as single ended inputs?
Thank You
Harsh
