Does the i2c channel of an external camera's mipi/csi connecting to Xavier NX ISP/VI has to be synched up with its data lanes?

There is an IMX247 mipi camera connecting to Xavier NX module. Looks like the camera’s response to the i2c commands is slower (due to the delay during the transmission) than its data lanes.
In another words, after the ISP of Xavier issuing a control command to trigger the video streaming out of the camera, the camera starts to send out the video stream to Xavier before the Xavier ISP to received the i2c acknowledge from camera. Does this cause any issues on Xavier side ?
For my observation, the Xavier reports error complaining it didn’t receive any response from camera. Here is the kernel message on Xavier:
[ 117.263675] [RCE] WARNING: t194/isp5.c:901 [config_channel] “All error notifications not enabled: correctable=0x00 uncorrectable=0x00”

[ 118.011809] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2

[ 120.111621] fence timeout on [ffffffc3b29856c0] after 1500ms

[ 120.111627] tegra194-vi5 15c10000. vi: no reply from camera processor

[ 120.111641] tegra194-vi5 15c10000. vi: vi capture get status failed

[ 120.111887] name=[nvhost_sync:39], current value=0 waiting value=1

Can someone explain why Xavier NX module can’t receive any reply from camera ?


Can below command run sucessfully?

v4l2-ctl --stream-mmap --stream-count=100 --set-ctrl bypass_mode=0 -d /dev/video0

Yes, this “v4l2-ctl” command works fine:
It can capture good raw image which was opened/displayed on my ms-windows10 with raw image editor.

It means that both i2c channel and data lanes are working fine in the context of “v4l2-ctl” command.

But when the gstreamer command “gst-launch-1.0” is launched, the video process goes a different route: it goes through Tegra’s ISP/VI components and causes these errors:
[ 120.111627] tegra194-vi5 15c10000. vi: no reply from camera processor
[ 120.111641] tegra194-vi5 15c10000. vi: vi capture get status failed

That’s why I suspected that ISP/VI couples the i2c and data lane which is timing sensitive. Correct me if I’m wrong.

This is the gstreamer command being used:
gst-launch-1.0 nvarguscamerasrc sensor-id=0 ! ‘video/x-raw(memory:NVMM), width=1920, height=1080, framerate=30/1’ ! nvvidconv flip-method=2 ! ‘video/x-raw, format=I420’ ! xvimagesink -e

What’s your BSP version? Did you have any integrate/modify the sensor driver?

On the left side is the good-old camera to Xavier connection via mipi interface, everything is working fine.
On the right side the data/clock lanes are re-route to my proprietary D-PHY chips but the I2C channel of the mipi take a short cut.

There is approximately 1ms delay between the i2c and the data lanes on Xavier mipi side. That’s why I’m wondering that the Tegra ISP does some kind of correlation between CCI/i2c and CSI/data-lane.
But due to the delay on the data lanes(re-route to Cyton D-PHYs), ISP got confused. Isn’t it ?

We bought the Xavier NX with IMX577 cameras from Leopard Imaging, Inc without any changes on BSP or Linux kernel(Ubuntu 18.04 TS)

It’s imx274 or imx577? That’s confuse

it’s imx577. imx274 was a typo.

Did you consult with Leopard for your question?

Yes, I did but no response from them( :-(

it’s indicated from the kernel dmesg that Tegra VI raised the warning.

Hi charles17,
Sorry for if we missed your Email. Could you send the Email again to both and
If you are also using our carrier board, we have drivers.