DP MST mode detection (driver-level vs. SOR register read) and MST hub IC bring-up reference — AGX Orin Industrial, custom carrier, L4T 36.4.4

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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  • Module: Jetson AGX Orin Industrial
  • JetPack: 6.2.1 (open to changing the version — if a specific release has better/officially-supported MST behavior, please advise)
  • L4T: 36.4.4
  • Carrier board: Custom carrier board

Hello,

We are developing a project on a custom carrier board based on the NVIDIA Jetson AGX Orin Industrial module. On the DisplayPort output we plan to use an MST hub IC (SUNIX DPH2001 family, DP 1.2 MST hub) to drive multiple displays from a single DP port.

We would like official guidance on how to determine whether the DP link is currently operating in MST mode (through the hub) vs. SST (direct connection), and we are looking at two approaches plus a hardware bring-up question.

1. Driver-level / runtime MST detection

  • On L4T R36.4.4, is there an official, programmatic way to query whether the current DP output is running in MST?
  • With the NVIDIA display driver, which path is supported — debugfs, sysfs, or DPCD via /dev/drm_dp_aux? For example, is there an interface to read MSTM_CTRL (DPCD 0x00111, MST_EN bit) or the branch device’s MSTM_CAP (DPCD 0x00021)?
  • We have seen that under X11 an MST link shows up as child outputs in xrandr (e.g., DP-0.3, DP-0.4) while the parent DP-0 is reported disconnected. Is this the recommended/expected way to detect MST, or is there a more direct API?

2. Register-level (TRM) MST detection
We checked the public Orin TRM (DP-10508-002 v1.2) and confirmed the following:

  • DisplayPort Multistream (MST) architecture and the SF/SOR description (Display Controller chapter)
  • Display register map: Display base 0x13800000, NV_PDISP_SOR region at +0xC000 (0x800 per SOR)
  • NV_PDISP_FE_CMGR_CLK_SOR_<i> (offset 0x2300 + i*0x800), with fields HEAD[15:12], STATE[23], LINK_SPEED[22:18]
  • NV_PDISP_FE_SW_SYS_CAP (HEAD_EXISTS/SOR_EXISTS)

However, the TRM does not document the SOR/SF DisplayPort link-layer registers (MST framing/enable, head→SOR stream assignment, time-slot / VC payload).

  • Question: Is there a SOR register/bit that indicates whether MST is active, that we can read (e.g., via devmem)? If so, could you provide the exact offset and bit field (valid for R36.4.4)? Since MST funnels multiple streams onto a single SOR, the documented CMGR_CLK_SOR register alone does not seem sufficient to distinguish “1 direct display” from “MST hub with multiple displays.”

3. MST hub IC bring-up reference

  • Are there official documents or samples for attaching a DP MST hub IC to the AGX Orin Industrial on a custom carrier board (device tree configuration, DP link training / bandwidth considerations, EDID handling, list of validated MST hubs)?
  • Is MST supported only on the X11 path, or also via DRM/KMS (e.g., nvdrmvideosink) on R36.4.4? We need to know the supported scope before we commit the hub IC into the hardware design.

Thank you for your help.

References we are working from

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Hello,

I am a colleague of the original poster.

Since English is not our native language, there may have been some ambiguity in the previous discussion. I would like to provide some additional context and clarification.

If necessary, we can create a new topic instead.

Our company has developed and deployed multiple custom carrier boards based on the NVIDIA Jetson AGX Orin platform across several projects.

Our current requirement is to drive two independent display windows from a single Orin module. During our investigation, we found that there do not appear to be any officially supported solutions or reference designs for this specific use case.

We would appreciate clarification on the following points:

  1. Are there any known limitations or restrictions when using a DisplayPort MST Hub IC to enable MST operation on Jetson AGX Orin?
  2. Based on several forum posts and successful user reports, we would also like to understand whether there is a requirement for the MST Hub IC to be powered on and fully operational before the Orin module begins its boot sequence.

For example, if the MST Hub powers up after the system has already booted, would there be any limitations regarding DisplayPort link training, topology discovery, EDID detection, or MST enumeration?

Any guidance on the expected behavior or recommended hardware design considerations would be greatly appreciated.

Thank you for your support.

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— 🤖 This is an automated AI response. I’m here to help, but please verify important details! —

I could not find clear support for that in the provided Jetson AGX Orin documentation.

— We support team will also look into your issue to have further suggestions soon. please stay tuned. —

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Hi,

Please try to run below steps to demo dual display sample code.

sudo apt update
sudo apt install nvidia-jetpack

Apply the patch from Display second screen using mmapi ex. 8 - #28 by DavidDDD.

And run the mmapi 08 sample code.

# single mode
./video_dec_drm ../../data/Video/sample_outdoor_car_1080p_10fps.h264 H264
# dual mode
./video_dec_drm dual  ../../data/Video/sample_outdoor_car_1080p_10fps.h264 H264

Thanks