DPHY skew difference between nvgstcapture-1.0 --sensor-id=0 and v4L2-ctl --device /dev/video0 --stream-mmap -c bypass_mode=0
Use command nvgstcapture-1.0 --sensor-id=0 . skew is right, and get image from camera.
The log is :
May 21 19:33:06 yt2mipi kernel: [12214.003606] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=2, csi=2)
May 21 19:33:06 yt2mipi kernel: [12214.007215] [RCE] MIPI clock = 2100000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
May 21 19:33:06 yt2mipi kernel: [12214.007219] [RCE] ===== NVCSI Stream Configuration =====
May 21 19:33:06 yt2mipi kernel: [12214.007221] [RCE] stream_id: PP 2, csi_port: PORT C
May 21 19:33:06 yt2mipi kernel: [12214.007224] [RCE] Brick: PHY 1, Mode: D-PHY
May 21 19:33:06 yt2mipi kernel: [12214.007227] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
May 21 19:33:06 yt2mipi kernel: [12214.007230] [RCE] Clock information:
May 21 19:33:06 yt2mipi kernel: [12214.007232] [RCE] MIPI clock rate: 2100.00 MHz
May 21 19:33:06 yt2mipi kernel: [12214.007235] [RCE] T_HS settle: 0, T_CLK settle: 0
May 21 19:33:06 yt2mipi kernel: [12214.007238] [RCE] ======================================
May 21 19:33:06 yt2mipi kernel: [12214.007241] [RCE] tegra_nvcsi_stream_open(vm0, stream=2, csi=2)
May 21 19:33:06 yt2mipi kernel: [12214.007244] [RCE] nvcsi_calc_ths_settle ths_settle 22
May 21 19:33:06 yt2mipi kernel: [12214.007246] [RCE] nvcsi_calc_ths_settle ths_settle 22
May 21 19:33:06 yt2mipi kernel: [12214.007249] [RCE] nvcsi_calc_ths_settle ths_settle 22
May 21 19:33:06 yt2mipi kernel: [12214.007252] [RCE] nvcsi_calc_tclk_settle tclk_settle 35
May 21 19:33:06 yt2mipi kernel: [12214.007255] [RCE] ISR PHY 1 CIL_A 0x110
May 21 19:33:06 yt2mipi kernel: [12214.007257] [RCE] ISR PHY 1 CIL_B 0x110
May 21 19:33:06 yt2mipi kernel: [12214.007260] [RCE] Deskew setup message sent for port 2 num_lane 4
May 21 19:33:06 yt2mipi kernel: [12214.007263] [RCE] nvcsi_calc_ths_settle ths_settle 22
May 21 19:33:06 yt2mipi kernel: [12214.007266] [RCE] nvcsi_calc_ths_settle ths_settle 22
May 21 19:33:06 yt2mipi kernel: [12214.007268] [RCE] nvcsi_calc_ths_settle ths_settle 22
May 21 19:33:06 yt2mipi kernel: [12214.007271] [RCE] nvcsi_calc_tclk_settle tclk_settle 35
May 21 19:33:07 yt2mipi kernel: [12214.129698] bwmgr API not supported
May 21 19:33:07 yt2mipi kernel: [12214.135717] bwmgr API not supported
May 21 19:33:07 yt2mipi kernel: [12214.464654] [RCE] ISR PHY 1 CIL_A 0xe000000
May 21 19:33:07 yt2mipi kernel: [12214.464662] [RCE] ISR PHY 1 CIL_B 0x6000000
v4L2-ctl --device /dev/video0 --stream-mmap -c bypass_mode=0 . skew is wrong. Don’t get the image from camera. The DTS and other configuration are same. Just run different command. I am confused.
How do I run the same skew of nvgstcapture-1.0 command, when I run the command v4L2-ctl?
The log is:
May 21 19:31:52 yt2mipi kernel: [12140.057854] [RCE] NVCSILP clock rate = 204000000 Hz.
May 21 19:31:52 yt2mipi kernel: [12140.057860] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=2, csi=2)
May 21 19:31:52 yt2mipi kernel: [12140.057863] [RCE] MIPI clock = 102000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
May 21 19:31:52 yt2mipi kernel: [12140.057865] [RCE] ===== NVCSI Stream Configuration =====
May 21 19:31:52 yt2mipi kernel: [12140.057868] [RCE] stream_id: PP 2, csi_port: PORT C
May 21 19:31:52 yt2mipi kernel: [12140.057871] [RCE] Brick: PHY 1, Mode: D-PHY
May 21 19:31:52 yt2mipi kernel: [12140.057873] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
May 21 19:31:52 yt2mipi kernel: [12140.057876] [RCE] Clock information:
May 21 19:31:52 yt2mipi kernel: [12140.057878] [RCE] MIPI clock rate: 102.00 MHz
May 21 19:31:52 yt2mipi kernel: [12140.057880] [RCE] T_HS settle: 0, T_CLK settle: 0
May 21 19:31:52 yt2mipi kernel: [12140.057883] [RCE] ======================================
May 21 19:31:52 yt2mipi kernel: [12140.057885] [RCE] tegra_nvcsi_stream_open(vm0, stream=2, csi=2)
May 21 19:31:52 yt2mipi kernel: [12140.057888] [RCE] nvcsi_calc_ths_settle ths_settle 54
May 21 19:31:52 yt2mipi kernel: [12140.057890] [RCE] nvcsi_calc_ths_settle ths_settle 54
May 21 19:31:52 yt2mipi kernel: [12140.057892] [RCE] nvcsi_calc_ths_settle ths_settle 54
May 21 19:31:52 yt2mipi kernel: [12140.057895] [RCE] nvcsi_calc_tclk_settle tclk_settle 35
May 21 19:31:53 yt2mipi kernel: [12140.617841] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.617847] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.617851] [RCE] ISR PHY 1 CIL_A 0x44
May 21 19:31:53 yt2mipi kernel: [12140.617854] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.617857] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.617860] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.617863] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.617867] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.617870] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.617873] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.617876] [RCE] ISR PHY 1 CIL_A 0x44
May 21 19:31:53 yt2mipi kernel: [12140.642143] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 131072
May 21 19:31:53 yt2mipi kernel: [12140.673864] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673870] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673871] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673873] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673874] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673875] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673876] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673877] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673878] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673880] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673881] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673882] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.673883] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673884] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673886] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673887] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673888] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673889] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673890] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673892] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673893] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673894] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673896] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673897] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.673898] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673899] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673900] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673901] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673903] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673904] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673905] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673906] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673907] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673908] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673910] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673911] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673912] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673913] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673914] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673915] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673917] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.673918] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673919] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.673920] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.673921] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673923] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.673924] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.675433] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 2, flags: 0, err_data 131072
May 21 19:31:53 yt2mipi kernel: [12140.729839] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.729844] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729846] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729847] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729848] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729850] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729851] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729852] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729853] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729854] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729855] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729857] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729858] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729859] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729860] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729861] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729863] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729864] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729865] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729866] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729867] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729868] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729870] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.729871] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729872] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729873] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729874] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729875] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729877] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729878] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729879] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729880] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729881] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729882] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729884] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729885] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.729886] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729887] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729888] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729889] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729891] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729892] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729893] [RCE] ISR PHY 1 CIL_A 0x40
May 21 19:31:53 yt2mipi kernel: [12140.729894] [RCE] ISR PHY 1 CIL_A 0x4
May 21 19:31:53 yt2mipi kernel: [12140.729895] [RCE] ISR PHY 1 CIL_A 0x40
What’s the version? Did you verify on JP5.1.3?
The version is R35.3.1
Please confirm by r35.5.0
Thanks
It’s difficult to change the version. We need to demo on the version and no redundancy soc.
Could you please tell me why the MIPI clock rate is 2100.00 MHz by nvgstcapture-1.0 ? Why the MIPI clock rate is 102.00 MHz by v4L2-ctl and how to set MIPI clock rate? Do they set different values in DTS?
Well, they should be the same. Both of them are calculate from the pix_clk_hz in device tree.
Do you have any modification in the CSI kernel driver?
We don’t modify CSI kernel driver. We add our serdes driver between camera and nvcsi in DTS by port.
Could you please tell me how to caculate MIPI clock rate from pix_clk_hz?
DTS:
serdes@6f {
compatible = “serdes”;
reg = <0x6f>;
ports {
port@0 {
reg = <0x00>;
endpoint {
port-index = <0x02>;
bus-width = <0x04>;
remote-endpoint = <0x287>;
phandle = <0x6b0>;
};
};
port@1 {
reg = <0x01>;
endpoint {
port-index = <0x02>;
bus-width = <0x04>;
remote-endpoint = <0x2c6>;
phandle = <0x6b1>;
};
};
};
mode0 {
vc_id = [30 00];
mclk_khz = “24000”;
num_lanes = [34 00];
tegra_sinterface = “serial_c”;
phy_mode = “DPHY”;
discontinuous_clk = “no”;
dpcm_enable = “false”;
cil_settletime = [30 00];
lane_polarity = [30 00];
active_w = “1920”;
active_h = “1080”;
mode_type = “bayer”;
pixel_phase = “rggb”;
csi_pixel_bit_depth = “12”;
dynamic_pixel_bit_depth = “12”;
readout_orientation = [30 00];
line_length = “2200”;
inherent_gain = [31 00];
mclk_multiplier = “6.1875”;
pix_clk_hz = “148500000”;
serdes_pix_clk_hz = “333333333”;
gain_factor = “10”;
min_gain_val = [30 00];
max_gain_val = “300”;
step_gain_val = [33 00];
default_gain = [30 00];
min_hdr_ratio = [31 00];
max_hdr_ratio = [31 00];
framerate_factor = “1000000”;
min_framerate = “30000000”;
max_framerate = “30000000”;
step_framerate = [31 00];
default_framerate = “30000000”;
exposure_factor = “1000000”;
min_exp_time = “59”;
max_exp_time = “33333”;
step_exp_time = [31 00];
default_exp_time = “33333”;
embedded_metadata_height = [31 00];
};
};
cam_0@10 {
compatible = "sensing,imx390_1";
reg = <0x10>;
devnode = "video1";
physical_w = "3.680";
physical_h = "2.760";
sensor_model = "imx390";
use_sensor_mode_id = "true";
reset-gpios = <0x5a 0xa1 0x00>;
phandle = <0x483>;
mode0 {
vc_id = [30 00];
mclk_khz = "24000";
num_lanes = [34 00];
tegra_sinterface = "serial_c";
phy_mode = "DPHY";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = [30 00];
lane_polarity = [30 00];
active_w = "1920";
active_h = "1080";
mode_type = "bayer";
pixel_phase = "rggb";
csi_pixel_bit_depth = "12";
dynamic_pixel_bit_depth = "12";
readout_orientation = [30 00];
line_length = "2200";
inherent_gain = [31 00];
mclk_multiplier = "6.1875";
pix_clk_hz = "148500000";
serdes_pix_clk_hz = "1400000000";
gain_factor = "10";
min_gain_val = [30 00];
max_gain_val = "300";
step_gain_val = [33 00];
default_gain = [30 00];
min_hdr_ratio = [31 00];
max_hdr_ratio = [31 00];
framerate_factor = "1000000";
min_framerate = "30000000";
max_framerate = "30000000";
step_framerate = [31 00];
default_framerate = "30000000";
exposure_factor = "1000000";
min_exp_time = "59";
max_exp_time = "33333";
step_exp_time = [31 00];
default_exp_time = "33333";
embedded_metadata_height = [31 00];
};
ports {
port@0 {
reg = <0x00>;
endpoint {
port-index = <0x02>;
bus-width = <0x04>;
remote-endpoint = <0x6b0>;
phandle = <0x287>;
};
};
};
};
For CPHY the mipi clock calculate by below formula. The serdes_pix_clk_hz will override the pix_clk_hz if define it in your dts.
mipi_clock = (pix_clk_hz * depth / num_lanes) * 7 / 16
What’s the formula for DPHY? We use DPHY.
Below is for DPHY calculation.
mipi_clock = (pix_clk_hz * depth / num_lanes) * 2
Thanks. Is the mipi_clock equal to DPHY rate?
Not exactly.
What’s the relation between DPHY rate and mipi_clock? If DPHY rate is 1Gbps, what’s the maxium mipi_clock.
I find the following formula in the (Sensor Software Driver Programming — NVIDIA Jetson Linux Developer Guide 1 documentation).
There is no *2. What’s the difference?
Output data rate = (sensor or deserializer pixel clock in hertz) * (bits per pixel) / (number of CSI lanes)
Please help to reply.
Usually, DPHY rate >= MIPI clock
The output data rate = mipi_clock*2 (due to double data rate).
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