We are finding excursions of the PLL thermal limit of 70degC when operating our Jetson Nano with passive cooling. This results in various Dmesg error logs, however, we are unsure if these excursions result in any performance throttling with the device ei. frequency scaling. We checked the “current EMC frequency” of the device before and after 70degC with cat /sys/kernel/debug/tegra_bwmgr/emc_rate however there was no change - We were originally assuming that the “DRAM Cooling” given in this table TABLE meant the EMC frequency was throttled when the thermal limit was met, but this does not seem to be the case.
Does anyone know the definition of “DRAM Cooling” in regards to the technical documentation provided by Nvidia?
those logs seem it’s worked.
when PLL temperature is > 70C, DRM cooling device is expected to be activated and start pooling DDR thermal state to decide EMC refresh rate based on temperature.
please also check below for confirmation.
for example,
I meant, it looks PLL temperature is dropping when it above 70C.
could you please dig into cur_state to confirm the DRM cooling device is actually activate or not.
thanks
Yes, I can confirm that the “tegra-dram” cooling device triggers (1) when above 71 Deg C.
But I still don’t understand the cooling mechanism. Namely, how the DRAM cooling influences temperature, and if those actions influence the performance of the product? For example, does it throttle frequency on a specific circuit or does it reduce the voltage?
it’s passive cooling; when PLL temperature crossed trip point temperature, then dram cooling device reads DDR Die-0 & Die-1 temperature state to decide self-refresh rate & EMC DVFS table.