Drive stength of CZ pads (SDMMC3_DAT3/GPIO3_PP02)

What is the maximum drive strength of CZ pads? According to the Jetson TX1 OEM Product Design Guide I would expect it to be 2mA, just as it is for ST pins. To drive with 2mA my understanding is, that up and down drive need to be set to 127 in SDMMC3_PAD_CFG. Is that correct?

We’re trying to use GPIO3_PP02, which uses the SDMMC3_DAT3 pad, as a GPIO output to control an ICs reset signal. Having an external 10k pull down on this pin, I can not get the pin above ~500mV level. If I leave the pin unconnected, so without any load it’s drive to 1.8V.

Looking in the debugfs, the drive values seemed to be set to 18 for up and down only:

# echo drive_sdmmc3 > /sys/kernel/debug/pinctrl/700008d4.pinmux/pinconf-pin-prop 
# cat /sys/kernel/debug/pinctrl/700008d4.pinmux/pinconf-pin-prop 
PinName: drive_sdmmc3
Pin Properties:

So we tried modifying pull-down-strength via device-tree. For this we added the following to our boards pinmux dtsi file:

/ {
	pinmux: pinmux@700008d4 {
		drive_default: drive {
			sdmmc3 {
				nvidia,pins = "drive_sdmmc3";
				nvidia,pull-down-strength = <127>;
				nvidia,pull-up-strength = <127>;

The updated DTB is flashed to the DTB partition using ./ -k DTB boardname mmcblk0p1, which apparently works. Now I had expected that CBoot would take care of applying these values.
Still after rebooting the strength values remain at 18.

I actually hacked something together to rewrite the SDMMC3_PAD_CFG register after the kernel is fully booted. This makes the values reported by /sys/kernel/debug/pinctrl/700008d4.pinmux/pinconf-pin-prop correct, but still the drive strength appears unchanged.

Am I missing anything here?

hello julianscheel,

it’s correct that drive strength is up to 2mA, you should have device tree configuration for the drive strength.
please refer to forum discussion thread, GPIO 417 drive strength configuration - #2 by JerryChang as see-also,

Thanks for getting back. Unfortunately as said, the device-tree change did not have any effect at all.
Also in the topic you reference I don’t see any further useful information for why the device-tree change would not have an effect.

Any thoughts on why the device-tree change would not lead to an actual change of the drive values written to the hardware registers?

hello julianscheel,

please check below pin descriptions for Jetson Nano System-on-Module.

CZ (controlled output impedance) pins are optimized for use in applications requiring tightly controlled output impedance.
They are similar to ST pins, except for changes in the drive strength circuitry and in the weak pull-ups/-downs.

CZ pins are included on the VDDIO_SDMMC1 and VDDIO_SDDMC3 power rails. Each of those rails also includes a pair of CZ_COMP pins. Circuitry within the Jetson module continually matches the output impedance of the CZ pins to the on-board pull-up/-down resistors attached to the CZ_COMP pins.

Just wanted to post a quick note on the actual fix, in case anyone else is running into the same issue:
I had the max77620_ldo6 (vddio-sdmmc3-ap) supply disabled, due to sdmmc3 being disabled. But in order to drive the SDMMC3_* pins as GPIOs it needs to be enabled.