This is my current config.
cuphycontroller_P5G_FXN.yaml
# Copyright (c) 2017-2024, NVIDIA CORPORATION. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification, are permitted
# provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright notice, this list of
# conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
# * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
# FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
# STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---
l2adapter_filename: l2_adapter_config_P5G.yaml
aerial_metrics_backend_address: 127.0.0.1:8081
# CPU core shared by all low-priority threads
low_priority_core: 8
nic_tput_alert_threshold_mbps: 85000
cuphydriver_config:
standalone: 0
validation: 0
num_slots: 8
profiler_sec: 0
log_level: DBG
dpdk_thread: 8
dpdk_verbose_logs: 0
accu_tx_sched_res_ns: 500
accu_tx_sched_disable: 0
fh_stats_dump_cpu_core: 8
pdump_client_thread: -1
mps_sm_pusch: 84
mps_sm_pucch: 16
mps_sm_prach: 16
mps_sm_pdsch: 82
mps_sm_pdcch: 28
mps_sm_pbch: 14
mps_sm_srs: 16
pdsch_fallback: 0
dpdk_file_prefix: cuphycontroller
nics:
- nic: 0000:ab:00.0
mtu: 8192
cpu_mbufs: 196608
uplane_tx_handles: 64
txq_count: 48
rxq_count: 16
txq_size: 8192
rxq_size: 16384
gpu: 1
gpus:
- 1
# Set GPUID to the GPU sharing the PCIe switch as NIC
# run nvidia-smi topo -m to find out which GPU
workers_ul:
- 2
- 3
workers_dl:
- 4
- 5
- 6
workers_sched_priority: 95
prometheus_thread: -1
start_section_id_srs: 3072
start_section_id_prach: 2048
enable_ul_cuphy_graphs: 1
enable_dl_cuphy_graphs: 1
# Both RF and eLSU eCPRI configs
ul_order_timeout_cpu_ns: 4000000
ul_order_timeout_gpu_ns: 4000000
cplane_disable: 0
gpu_init_comms_dl: 1
cell_group: 1
cell_group_num: 1
pusch_sinr: 1
pusch_rssi: 1
pusch_tdi: 0
pusch_cfo: 0
pusch_dftsofdm: 0
pusch_to: 0
pusch_select_eqcoeffalgo: 1
pusch_select_chestalgo: 1
pusch_tbsizecheck: 1
enable_cpu_task_tracing: 0
enable_compression_tracing: 0
enable_prepare_tracing: 0
enable_dl_cqe_tracing: 0
mMIMO_enable: 0
pusch_forcedNumCsi2Bits: 0
enable_srs: 0
mCh_segment_proc_enable: 0
enable_csip2_v3: 0
cells:
- name: O-RU 0
cell_id: 101
ru_type: 1
# set to 00:00:00:00:00:00 to use the MAC address of the NIC port to use
src_mac_addr: 9c:63:c0:a7:08:32
# dst_mac_addr: e8:c7:4f:25:89:40 # MAC address of Foxconn O-RU #1 # Liteon
dst_mac_addr: 6c:b9:c5:22:92:cc
nic: 0000:ab:00.0
vlan: 564
pcp: 0
txq_count_uplane: 1
eAxC_id_ssb_pbch: [0, 1, 2, 3]
eAxC_id_pdcch: [0, 1, 2, 3]
eAxC_id_pdsch: [0, 1, 2, 3]
eAxC_id_csirs: [0, 1, 2, 3]
eAxC_id_pusch: [0, 1, 2, 3]
eAxC_id_pucch: [0, 1, 2, 3]
eAxC_id_srs: [0, 1, 2, 3]
eAxC_id_prach: [0, 1, 2, 3]
dl_iq_data_fmt: {comp_meth: 1, bit_width: 9}
ul_iq_data_fmt: {comp_meth: 1, bit_width: 9}
section_3_time_offset: 484
fs_offset_dl: 15
exponent_dl: 4
ref_dl: 0
fs_offset_ul: -5
exponent_ul: 4
max_amp_ul: 65504
mu: 1
T1a_max_up_ns: 280000
T1a_max_cp_ul_ns: 405000
Ta4_min_ns: 50000
Ta4_max_ns: 331000
Tcp_adv_dl_ns: 125000
fh_len_range: 0
pusch_prb_stride: 273
prach_prb_stride: 12
srs_prb_stride: 273
pusch_ldpc_max_num_itr_algo_type: 1
pusch_fixed_max_num_ldpc_itrs: 10
pusch_ldpc_n_iterations: 10
pusch_ldpc_early_termination: 0
pusch_ldpc_algo_index: 0
pusch_ldpc_flags: 2
pusch_ldpc_use_half: 1
ul_gain_calibration: 48.68
lower_guard_bw: 845
tv_pusch: cuPhyChEstCoeffs.h5
l2_adapter_config_P5G.yaml
# Copyright (c) 2017-2024, NVIDIA CORPORATION. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification, are permitted
# provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright notice, this list of
# conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
# * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
# FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
# STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---
#gnb_module
msg_type: scf_5g_fapi
phy_class: scf_5g_fapi
slot_advance: 3
# tick_generator_mode: 0 - poll + sleep; 1 - sleep; 2 - timer_fd
tick_generator_mode: 1
# Allowed maximum latency of SLOT FAPI messages which send from L2 to L1. Unit: slot
allowed_fapi_latency: 0
# Allowed tick interval error. Unit: us
allowed_tick_error: 10
timer_thread_config:
name: timer_thread
cpu_affinity: 7
sched_priority: 99
message_thread_config:
name: msg_processing
#core assignment
cpu_affinity: 7
# thread priority
sched_priority: 95
# Lowest TTI for Ticking
mu_highest: 1
dl_tb_loc: 1
instances:
# PHY 0
-
name: scf_gnb_configure_module_0_instance_0
prach_ta_offset_usec: 2.5
-
name: scf_gnb_configure_module_0_instance_1
prach_ta_offset_usec: 2.5
-
name: scf_gnb_configure_module_0_instance_2
prach_ta_offset_usec: 2.5
-
name: scf_gnb_configure_module_0_instance_3
prach_ta_offset_usec: 2.5
-
name: scf_gnb_configure_module_0_instance_4
prach_ta_offset_usec: 2.5
-
name: scf_gnb_configure_module_0_instance_5
prach_ta_offset_usec: 2.5
-
name: scf_gnb_configure_module_0_instance_6
prach_ta_offset_usec: 2.5
-
name: scf_gnb_configure_module_0_instance_7
prach_ta_offset_usec: 2.5
# Config dedicated yaml file for nvipc. Example: nvipc_multi_instances.yaml
nvipc_config_file: null
# Transport settings for nvIPC
transport:
type: shm
udp_config:
local_port: 38556
remort_port: 38555
shm_config:
primary: 1
prefix: nvipc
cuda_device_id: 0
ring_len: 8192
mempool_size:
cpu_msg:
buf_size: 8192
pool_len: 4096
cpu_data:
buf_size: 576000
pool_len: 1024
cuda_data:
buf_size: 307200
pool_len: 0
gpu_data:
buf_size: 576000
pool_len: 0
dpdk_config:
primary: 1
prefix: nvipc
local_nic_pci: 0000:ab:00.0
peer_nic_mac: 00:00:00:00:00:00
cuda_device_id: 0
need_eal_init: 0
lcore_id: 11
mempool_size:
cpu_msg:
buf_size: 8192
pool_len: 4096
cpu_data:
buf_size: 576000
pool_len: 1024
cuda_data:
buf_size: 307200
pool_len: 0
app_config:
grpc_forward: 0
debug_timing: 0
pcap_enable: 1
pcap_cpu_core: 8 # CPU core of background pcap log save thread
pcap_cache_size_bits: 29 # 2^29 = 512MB, size of /dev/shm/${prefix}_pcap
pcap_file_size_bits: 31 # 2^31 = 2GB, max size of /var/log/aerial/${prefix}_pcap. Requires pcap_file_size_bits > pcap_cache_size_bits.
pcap_max_data_size: 8000 # Max DL/UL FAPI data size to capture reduce pcap size.
cell_group: 1
prepone_h2d_copy: 1
pucch_dtx_thresholds: [-100.0, -100.0, -100.0, -100.0, -100.0]
ptp: {gps_alpha: 0, gps_beta: 0}
enableTickDynamicSfnSlot: 1
...
