DSI display on the TX1

Hi WayneWWW,
Now I have commented on the regulator. Now how to solve the problem of "dsi: Tlpx mipi range violated"and “dsi: mipi range violated”.

[    2.084768] tegradc tegradc.0: Display dc.54200000 registered with id=0
[    2.090486] of_dc_parse_platform_data: DC OR node is connected to /host1x/dsi
[    2.097735] display board info: id 0x0, fab 0x0
[    2.102640] display board info: id 0x0, fab 0x0
[    2.107022] of_dc_parse_platform_data: could not find vrr-settings node
[    2.113209] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present
[    2.119783] of_dc_parse_platform_data: could not find cmu node for adobeRGB
[    2.126889] tegradc tegradc.0: DT parsed successfully
[    2.132166] tegradc tegradc.0: DSI: HS clock rate is 81000
[    2.139054] tegradc tegradc.0: nominal-pclk:27000000 parent:27000000 div:1.0 pclk:27000000 26730000~29430000
[    2.211637] tegra_mipi_cal 700e3000.mipical: Mipi cal timeout,val:40013980, lanes:c0000000
[    2.217910] tegra_mipi_cal 700e3000.mipical: MIPI_CAL_CTRL                  0x00 0x2a000000
[    2.226255] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS            0x08 0x40013980
[    2.234557] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS_2          0x0c 0x00000020
[    2.242888] tegra_mipi_cal 700e3000.mipical: CILA_MIPI_CAL_CONFIG           0x14 0x00000000
[    2.251185] tegra_mipi_cal 700e3000.mipical: CILB_MIPI_CAL_CONFIG           0x18 0x00000000
[    2.259515] tegra_mipi_cal 700e3000.mipical: CILC_MIPI_CAL_CONFIG           0x1c 0x00000000
[    2.267847] tegra_mipi_cal 700e3000.mipical: CILD_MIPI_CAL_CONFIG           0x20 0x00000000
[    2.276156] tegra_mipi_cal 700e3000.mipical: CILE_MIPI_CAL_CONFIG           0x24 0x00000000
[    2.284495] tegra_mipi_cal 700e3000.mipical: CILF_MIPI_CAL_CONFIG           0x28 0x00000000
[    2.292796] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG           0x38 0x00000000
[    2.301105] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG           0x3c 0x00000000
[    2.309448] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG           0x40 0x00200200
[    2.317756] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG           0x44 0x00000200
[    2.326088] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG0             0x58 0x00000000
[    2.334396] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG1             0x5c 0x00000300
[    2.342728] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG2             0x60 0x00010010
[    2.351024] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG_2         0x64 0x00000000
[    2.359354] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG_2         0x68 0x00000000
[    2.367687] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG_2         0x70 0x00200002
[    2.375998] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG_2         0x74 0x00000002
[    2.978376] tegradc tegradc.0: dsi: Tlpx mipi range violated
[    2.982053] tegradc tegradc.0: dsi: mipi range violated
[    2.987359] tegradc tegradc.0: probed
[    3.071335] tegradc tegradc.0: nominal-pclk:27000000 parent:81000000 div:3.0 pclk:27000000 26730000~29430000
[    3.074664] Console: switching to colour frame buffer device 90x36
[    3.091915] tegradc tegradc.0: fb registered

Thanks

Could you check what value is violated in Tlpx checking?

Your panel setting seems a 50fps one. Is this what you wanted?

Yes,720x576@50hz. I print out the value.

printk(KERN_ALERT"clk_ps=%d dsi->info.fpga_freq_khz=%d phy_timing->t_tlpx=%d\n", clk_ps, dsi->info.fpga_freq_khz, phy_timing->t_tlpx);
	err = CHECK_RANGE(
	DSI_CONVERT_T_PHY_TO_T_PHY_PS(
			phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC),
			MIPI_T_TLPX_PS_MIN, MIPI_T_TLPX_PS_MAX);
	if (err < 0) {
		dev_warn(&dsi->dc->ndev->dev,
			"dsi: Tlpx mipi range violated\n");
		goto fail;
	}

Print information

[[    2.401466] tegra_get_platform=0
[    2.402725] clk_ps=50010 dsi->info.fpga_freq_khz=0 phy_timing->t_tlpx=0
[    2.757881] tegra_get_platform=0
[    2.759115] clk_ps=6173 dsi->info.fpga_freq_khz=0 phy_timing->t_tlpx=0
[    2.765648] tegradc tegradc.0: dsi: Tlpx mipi range violated
[    2.771251] tegradc tegradc.0: dsi: mipi range violated
[    2.776577] tegradc tegradc.0: probed

I also found that clk_ps is changing.
This is my dts configuration

dsi {
			status = "okay";
			nvidia,dsi-controller-vs = <DSI_VS_1>;
			panel-s-wqxga-10-1 {
			status = "okay";
				nvidia,dsi-lvds-bridge= <TEGRA_DSI_ENABLE>;
				compatible = "s,wqxga-10-1";
				nvidia,dsi-instance = <DSI_INSTANCE_0>;
				nvidia,dsi-n-data-lanes = <4>;
				nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
				nvidia,dsi-refresh-rate = <50>;
				nvidia,dsi-rated-refresh-rate = <50>;
				nvidia,dsi-te-polarity-low = <TEGRA_DSI_ENABLE>;
				nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
				nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
                nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END>;
		nvidia,dsi-ganged-type =<TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD>;//TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT
				nvidia,dsi-controller-vs = <DSI_VS_1>;
				nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
				nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
				nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
				nvidia,dsi-lp00-pre-panel-wakeup = <TEGRA_DSI_ENABLE>;
				nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
				nvidia,dsi-suspend-aggr = <DSI_HOST_SUSPEND_LV2>;
		nvidia,dsi-init-cmd =
		/* Long  Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
		/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
		/* For DSI packets each DT cell is interpreted as u8 not u32 */

			<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0x10 0x00 0x2A 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 20>,
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 20>,
			<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0x10 0x01 0x01 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 20>,
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 20>,
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_TEARING_EFFECT_ON 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 20>,
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 120>,
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 20>;
		nvidia,dsi-n-init-cmd = <14>;
		nvidia,dsi-suspend-cmd =
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 50>,
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 200>,
			<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_TEARING_EFFECT_OFF 0x0 0x0>,
			<TEGRA_DSI_DELAY_MS 20>;
		nvidia,dsi-n-suspend-cmd = <6>;

				disp-default-out {
					nvidia,out-type = <TEGRA_DC_OUT_DSI>;
					nvidia,out-width = <216>;
					nvidia,out-height = <135>;
					nvidia,out-flags = <TEGRA_DC_OUT_ONE_SHOT_MODE TEGRA_DC_OUT_ONE_SHOT_LP_MODE>;
					nvidia,out-parent-clk = "pll_d_out0";
					nvidia,out-xres = <720>;
					nvidia,out-yres = <576>;
				};
				display-timings {
					720x576-32 {
						clock-frequency = <27000000>;
						hactive = <720>;
						vactive = <576>;
						hfront-porch = <12>;
						hback-porch = <68>;
						hsync-len = <64>;
						vfront-porch = <5>;
						vback-porch = <39>;
						vsync-len = <5>;
						nvidia,h-ref-to-sync = <1>;
						nvidia,v-ref-to-sync = <1>;
					};
				};
				smartdimmer {
					status = "okay";
					nvidia,use-auto-pwm = <0>;
					nvidia,hw-update-delay = <0>;
					nvidia,bin-width = <0xffffffff>;
					nvidia,aggressiveness = <5>;

hi DaneLLL,
Thank you very much.
Now my print information is as follows.

[    2.085444] tegradc tegradc.0: Display dc.54200000 registered with id=0
[    2.091197] of_dc_parse_platform_data: DC OR node is connected to /host1x/dsi
[    2.098452] display board info: id 0x0, fab 0x0
[    2.103370] display board info: id 0x0, fab 0x0
[    2.107718] of_dc_parse_platform_data: could not find vrr-settings node
[    2.113921] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present
[    2.120497] of_dc_parse_platform_data: could not find cmu node for adobeRGB
[    2.127531] tegradc tegradc.0: DT parsed successfully
[    2.132936] tegradc tegradc.0: DSI: HS clock rate is 445500
[    2.139852] tegradc tegradc.0: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
[    2.208211] tegra_get_platform=0
[    2.209447] clk_ps=50010 dsi->info.fpga_freq_khz=0 phy_timing->t_tlpx=0
[    2.221865] tegra_mipi_cal 700e3000.mipical: Mipi cal timeout,val:40014980, lanes:c0000000
[    2.228136] tegra_mipi_cal 700e3000.mipical: MIPI_CAL_CTRL                  0x00 0x2a000000
[    2.236465] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS            0x08 0x40014980
[    2.244805] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS_2          0x0c 0x00000020
[    2.253105] tegra_mipi_cal 700e3000.mipical: CILA_MIPI_CAL_CONFIG           0x14 0x00000000
[    2.261412] tegra_mipi_cal 700e3000.mipical: CILB_MIPI_CAL_CONFIG           0x18 0x00000000
[    2.269757] tegra_mipi_cal 700e3000.mipical: CILC_MIPI_CAL_CONFIG           0x1c 0x00000000
[    2.278064] tegra_mipi_cal 700e3000.mipical: CILD_MIPI_CAL_CONFIG           0x20 0x00000000
[    2.286397] tegra_mipi_cal 700e3000.mipical: CILE_MIPI_CAL_CONFIG           0x24 0x00000000
[    2.294704] tegra_mipi_cal 700e3000.mipical: CILF_MIPI_CAL_CONFIG           0x28 0x00000000
[    2.303035] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG           0x38 0x00000000
[    2.311333] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG           0x3c 0x00000000
[    2.319663] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG           0x40 0x00200200
[    2.327996] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG           0x44 0x00000200
[    2.336304] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG0             0x58 0x00000000
[    2.344635] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG1             0x5c 0x00000300
[    2.352944] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG2             0x60 0x00010010
[    2.361252] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG_2         0x64 0x00000000
[    2.369595] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG_2         0x68 0x00000000
[    2.377903] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG_2         0x70 0x00200002
[    2.386235] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG_2         0x74 0x00000002
[    2.401485] tegra_get_platform=0
[    2.402743] clk_ps=50010 dsi->info.fpga_freq_khz=0 phy_timing->t_tlpx=0
[    2.415094] dsi2lvds_config_lvds value=122
[    2.417196] dsi ttttt
[    2.757883] tegra_get_platform=0
[    2.759118] clk_ps=1124 dsi->info.fpga_freq_khz=0 phy_timing->t_tlpx=6
[    2.765752] tegradc tegradc.0: probed
[    2.848485] tegradc tegradc.0: nominal-pclk:148345000 parent:444998438 div:3.0 pclk:148332812 146861550~161696050
[    2.864617] Console: switching to colour frame buffer device 240x67
[    2.894444] tegradc tegradc.0: fb registered
[    2.898834] tegradc tegradc.1: Display dc.54240000 registered with id=1
[    2.905264] of_dc_parse_platform_data: DC OR node is connected to /host1x/sor1
[    2.912637] parse_tmds_config: No tmds-config node
[    2.917301] of_dc_parse_platform_data: could not find vrr-settings node
[    2.923794] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present

Is not DSI has been fully configured? But I still did not output.

I found a problem.Why would there be different results, the same boot file?

I think you have modified the timing to make “Tlpx mipi range violated” pass. However, it is still wrong. I wonder if you can try DSI output first and then start to use dsi2lvds bridge.

Hi WayneWWW,
I found 720 x576 will appear this error"Tlpx mipi range violated" . Now i changed to 1920x1080 does not appear this error.
I think now is the DSI out problem. What do you think of how to check.

  • Can you help me look at the code?
    arch/arm/boot/dts/panel-s-wqxga-10-1.dtsi

    #include <dt-bindings/display/tegra-dc.h>
    #include <dt-bindings/display/tegra-panel.h>
    
    / {
    	host1x {
    		dsi {
    			status = "okay";
    			nvidia,dsi-controller-vs = <DSI_VS_1>;
    			panel-s-wqxga-10-1 {
    			status = "okay";
    				nvidia,dsi-lvds-bridge= <TEGRA_DSI_ENABLE>;
    				compatible = "s,wqxga-10-1";
    				nvidia,dsi-instance = <DSI_INSTANCE_0>;
    				nvidia,dsi-n-data-lanes = <4>;
    				nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
    				nvidia,dsi-refresh-rate = <60>;
    				//nvidia,dsi-rated-refresh-rate = <50>;
    				nvidia,dsi-te-polarity-low = <TEGRA_DSI_ENABLE>;
    				nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
    				nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
                                    nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END>;
    				nvidia,dsi-ganged-type =              <TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD>;
    				nvidia,dsi-controller-vs = <DSI_VS_1>;
    				nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
    				nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
    				nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
    				nvidia,dsi-lp00-pre-panel-wakeup = <TEGRA_DSI_ENABLE>;
    				nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
    				nvidia,dsi-suspend-aggr = <DSI_HOST_SUSPEND_LV2>;
                                    nvidia,dsi-pkt-seq =
    		         <CMD_VS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    			 <CMD_VE LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    			 <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    			 <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
    			 <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    			 <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;
    disp-default-out {
    					nvidia,out-type = <TEGRA_DC_OUT_DSI>;
    					nvidia,out-width = <217>;
    					nvidia,out-height = <135>;
    					nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
    					nvidia,out-parent-clk = "pll_d_out0";
    					nvidia,out-xres = <1920>;
    					nvidia,out-yres = <1080>;
    				};
    				display-timings {
    					1920x1080-32 {
    						clock-frequency = <148500000>;
    						hactive = <1920>;
    						vactive = <1080>;
    						hfront-porch = <88>;
    						hback-porch = <148>;
    						hsync-len = <44>;
    						vfront-porch = <4>;
    						vback-porch = <36>;
    						vsync-len = <5>;
    						nvidia,h-ref-to-sync = <1>;
    						nvidia,v-ref-to-sync = <1>;
    					};
    				};
    				smartdimmer {
    					status = "okay";
    					nvidia,use-auto-pwm = <0>;
    					nvidia,hw-update-delay = <0>;
    					nvidia,bin-width = <0xffffffff>;
    					nvidia,aggressiveness = <5>;
    					nvidia,use-vid-luma = <0>;
    					nvidia,phase-in-settings = <0>;
    					nvidia,phase-in-adjustments = <0>;
    					nvidia,k-limit-enable = <1>;
    					nvidia,k-limit = <200>;
    					nvidia,sd-window-enable = <0>;
    					nvidia,soft-clipping-enable= <1>;
    					nvidia,soft-clipping-threshold = <128>;
    					nvidia,smooth-k-enable = <1>;
    					nvidia,smooth-k-incr = <4>;
    					nvidia,coeff = <5 9 2>;
    					nvidia,fc = <0 0>;
    					nvidia,blp = <1024 255>;
    					nvidia,bltf = <57 65 73 82
    						       92 103 114 125
    						       138 150 164 178
    						       193 208 224 241>;
    					nvidia,lut = <255 255 255
    						      199 199 199
    						      153 153 153
    						      116 116 116
    						      85 85 85
    						      59 59 59
    						      36 36 36
    						      17 17 17
    						      0 0 0>;
    					nvidia,use-vpulse2 = <1>;
    					nvidia,bl-device-name = "pwm-backlight";
    				};
    				cmu {
    					nvidia,cmu-csc = < 0x138 0x3ba 0x00d
    							   0x3f5 0x120 0x3e6
    							   0x3fe 0x3f8 0x0e9 >;
    					nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6
    							    7 8 9 10 11 11 12 13
    							    13 14 15 15 16 17 17 18
    							    18 19 19 20 20 21 21 22
    							    22 23 23 23 24 24 24 25
    							    25 25 26 26 26 27 27 27
    							    28 28 28 28 29 29 29 29
    							    30 30 30 30 31 31 31 31
    							    32 32 32 32 33 33 33 33
    							    34 34 34 35 35 35 35 36
    							    36 36 37 37 37 37 38 38
    							    38 39 39 39 39 40 40 40
    							    41 41 41 41 42 42 42 43
    							    43 43 43 44 44 44 45 45
    							    45 45 46 46 46 46 47 47
    							    47 47 48 48 48 48 49 49
    							    49 49 50 50 50 50 50 51
    							    51 51 51 52 52 52 52 52
    							    53 53 53 53 53 53 54 54
    							    54 54 54 55 55 55 55 55
    							    55 56 56 56 56 56 56 57
    							    57 57 57 57 57 57 58 58
    							    58 58 58 58 59 59 59 59
    							    59 59 59 60 60 60 60 60
    							    60 60 61 61 61 61 61 61
    							    61 62 62 62 62 62 62 62
    							    63 63 63 63 63 63 63 64
    							    64 64 64 64 64 64 65 65
    							    65 65 65 65 66 66 66 66
    							    66 66 66 67 67 67 67 67
    							    67 68 68 68 68 68 68 69
    							    69 69 69 69 69 70 70 70
    							    70 70 70 71 71 71 71 71
    							    71 72 72 72 72 72 72 73
    							    73 73 73 73 73 74 74 74
    							    74 74 74 74 75 75 75 75
    							    75 75 76 76 76 76 76 76
    							    77 77 77 77 77 77 77 78
    							    78 78 78 78 78 79 79 79
    							    79 79 79 79 80 80 80 80
    							    80 80 80 80 81 81 81 81
    							    81 81 81 82 82 82 82 82
    							    82 82 82 83 83 83 83 83
    							    83 83 83 83 84 84 84 84
    							    84 84 84 84 85 85 85 85
    							    85 85 85 85 85 85 86 86
    							    86 86 86 86 86 86 86 86
    							    87 87 87 87 87 87 87 87
    							    87 87 88 88 88 88 88 88
    							    88 88 88 88 88 88 89 89
    							    89 89 89 89 89 89 89 89
    							    89 89 90 90 90 90 90 90
    							    90 90 90 90 90 90 91 91
    							    91 91 91 91 91 91 91 91
    							    91 91 91 92 92 92 92 92
    							    92 92 92 92 92 92 92 92
    							    93 93 93 93 93 93 93 93
    							    93 93 93 93 93 93 94 94
    							    94 94 94 94 94 94 94 94
    							    94 94 94 94 95 95 95 95
    							    95 95 95 95 95 95 95 95
    							    95 96 96 96 96 96 96 96
    							    96 96 96 96 96 96 97 97
    							    97 97 97 97 97 97 97 97
    							    98 99 99 100 101 101 102 103
    							    103 104 105 105 106 107 107 108
    							    109 110 110 111 112 112 113 114
    							    114 115 115 116 117 117 118 119
    							    119 120 120 121 121 122 123 123
    							    124 124 125 125 126 126 127 128
    							    128 129 129 130 130 131 131 132
    							    132 133 133 134 134 135 135 136
    							    136 137 138 138 139 139 140 140
    							    141 141 142 142 143 143 144 144
    							    144 145 145 146 146 147 147 148
    							    148 149 149 150 150 151 151 152
    							    152 153 153 153 154 154 155 155
    							    156 156 157 157 157 158 158 159
    							    159 160 160 160 161 161 162 162
    							    162 163 163 164 164 164 165 165
    							    165 166 166 167 167 167 168 168
    							    168 169 169 169 170 170 171 171
    							    171 172 172 172 173 173 173 174
    							    174 174 175 175 175 176 176 176
    							    177 177 177 178 178 178 179 179
    							    179 180 180 180 181 181 181 182
    							    182 182 183 183 183 184 184 184
    							    185 185 185 185 186 186 186 187
    							    187 187 188 188 188 189 189 189
    							    190 190 190 191 191 191 191 192
    							    192 192 193 193 193 194 194 194
    							    195 195 195 195 196 196 196 197
    							    197 197 198 198 198 199 199 199
    							    199 200 200 200 201 201 201 202
    							    202 202 203 203 203 203 204 204
    							    204 205 205 205 206 206 206 207
    							    207 207 208 208 208 208 209 209
    							    209 210 210 210 211 211 211 212
    							    212 212 213 213 213 214 214 214
    							    215 215 215 215 216 216 216 217
    							    217 217 218 218 218 219 219 219
    							    220 220 220 220 221 221 221 222
    							    222 222 222 223 223 223 224 224
    							    224 224 225 225 225 226 226 226
    							    226 227 227 227 227 228 228 228
    							    229 229 229 229 230 230 230 230
    							    230 231 231 231 231 232 232 232
    							    232 233 233 233 233 234 234 234
    							    234 234 235 235 235 235 236 236
    							    236 236 236 237 237 237 237 238
    							    238 238 238 238 239 239 239 239
    							    239 240 240 240 240 240 241 241
    							    241 241 241 242 242 242 242 243
    							    243 243 243 243 244 244 244 244
    							    244 245 245 245 245 245 246 246
    							    246 246 246 247 247 247 247 248
    							    248 248 248 248 249 249 249 249
    							    250 250 250 250 251 251 251 251
    							    251 252 252 252 253 253 253 253
    							    254 254 254 254 255 255 255 255 >;
    				};
    			};
    		};
    	};
    	backlight {
    		panel-s-wqxga-10-1-bl {
    			status = "disabled";
    			compatible = "s,wqxga-10-1-bl";
    			pwms = <&tegra_pwm 1 1000000>;
    			max-brightness = <255>;
    			default-brightness = <224>;
    			bl-measured = < 0 1 2 3 4 5 6 7
    					8 9 11 11 12 13 14 15
    					16 17 18 19 20 21 21 22
    					23 24 25 26 27 28 29 30
    					31 32 32 33 34 35 36 37
    					38 39 40 41 42 43 43 44
    					45 46 47 48 49 50 51 52
    					53 54 54 55 56 57 58 59
    					60 61 62 63 63 64 65 66
    					67 68 69 70 71 72 73 74
    					75 76 77 78 79 80 80 81
    					82 83 84 85 86 87 88 89
    					90 91 92 93 94 95 96 97
    					98 99 100 101 102 103 104 105
    					106 107 108 109 110 111 112 113
    					114 115 116 117 118 119 120 121
    					122 123 124 125 126 127 128 129
    					130 131 132 133 134 135 136 137
    					138 140 141 142 143 144 145 146
    					147 148 149 150 151 152 153 154
    					155 156 157 158 159 160 161 162
    					163 164 165 166 167 168 169 170
    					171 172 173 174 175 177 178 179
    					180 181 182 183 184 185 186 187
    					188 189 190 191 192 193 194 195
    					196 197 198 200 201 202 203 204
    					205 206 207 208 209 210 211 212
    					213 214 215 217 218 219 220 221
    					222 223 224 225 226 227 228 229
    					230 231 232 234 235 236 237 238
    					239 240 241 242 243 244 245 246
    					248 249 250 251 252 253 254 255 >;
    		};
    	};
    };
    

    arch/arm/mach-tegra/panel-s-wqxga-10-1.c

    /*
     * arch/arm/mach-tegra/panel-s-wqxga-10-1.c
     *
     * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved..
     *
    
    
    #include <mach/dc.h>
    #include <linux/delay.h>
    #include <linux/gpio.h>
    #include <linux/regulator/consumer.h>
    
    #include "board.h"
    #include "board-panel.h"
    #include "devices.h"
    #include "gpio-names.h"
    
    #define DSI_PANEL_RESET		1
    
    //static bool reg_requested;
    static struct regulator *avdd_lcd_3v3;
    static struct regulator *vdd_lcd_bl;
    static struct regulator *vdd_lcd_bl_en;
    static struct regulator *dvdd_lcd_1v8;
    static u16 en_panel_rst;
    #if 0
    static int dalmore_dsi_regulator_get(struct device *dev)
    {
    	int err = 0;
    
    	if (reg_requested)
    		return 0;
    	dvdd_lcd_1v8 = regulator_get(dev, "dvdd_lcd");
    	if (IS_ERR(dvdd_lcd_1v8)) {
    		pr_err("dvdd_lcd regulator get failed\n");
    		err = PTR_ERR(dvdd_lcd_1v8);
    		dvdd_lcd_1v8 = NULL;
    		goto fail;
    	}
    	avdd_lcd_3v3 = regulator_get(dev, "avdd_lcd");
    	if (IS_ERR(avdd_lcd_3v3)) {
    		pr_err("avdd_lcd regulator get failed\n");
    		err = PTR_ERR(avdd_lcd_3v3);
    		avdd_lcd_3v3 = NULL;
    		goto fail;
    	}
    
    	vdd_lcd_bl = regulator_get(dev, "vdd_lcd_bl");
    	if (IS_ERR(vdd_lcd_bl)) {
    		pr_err("vdd_lcd_bl regulator get failed\n");
    		err = PTR_ERR(vdd_lcd_bl);
    		vdd_lcd_bl = NULL;
    		goto fail;
    	}
    
    	vdd_lcd_bl_en = regulator_get(dev, "vdd_lcd_bl_en");
    	if (IS_ERR(vdd_lcd_bl_en)) {
    		pr_err("vdd_lcd_bl_en regulator get failed\n");
    		err = PTR_ERR(vdd_lcd_bl_en);
    		vdd_lcd_bl_en = NULL;
    		goto fail;
    	}
    	reg_requested = true;
    	return 0;
    fail:
    	return err;
    }
    #endif
    static int dsi_s_wqxga_10_1_postpoweron(struct device *dev)
    {
    	int err = 0;
    
    	//err = dalmore_dsi_regulator_get(dev);
    	//if (err < 0) {
    	//	pr_err("dsi regulator get failed\n");
    	//	goto fail;
    	//}
    
    	err = tegra_panel_gpio_get_dt("s,wqxga-10-1", &panel_of);
    	if (err < 0) {
    		pr_err("dsi gpio request failed\n");
    		goto fail;
    	}
    
    	/* If panel rst gpio is specified in device tree,
    	 * use that.
    	 */
    	if (gpio_is_valid(panel_of.panel_gpio[TEGRA_GPIO_RESET]))
    		en_panel_rst = panel_of.panel_gpio[TEGRA_GPIO_RESET];
    
    	if (dvdd_lcd_1v8) {
    		err = regulator_enable(dvdd_lcd_1v8);
    		if (err < 0) {
    			pr_err("dvdd_lcd regulator enable failed\n");
    			goto fail;
    		}
    	}
    
    	if (avdd_lcd_3v3) {
    		err = regulator_enable(avdd_lcd_3v3);
    		if (err < 0) {
    			pr_err("avdd_lcd regulator enable failed\n");
    			goto fail;
    		}
    	}
    
    	/* panel ic requirement after vcc enable */
    	msleep(260);
    
    	if (vdd_lcd_bl) {
    		err = regulator_enable(vdd_lcd_bl);
    		if (err < 0) {
    			pr_err("vdd_lcd_bl regulator enable failed\n");
    			goto fail;
    		}
    	}
    
    	if (vdd_lcd_bl_en) {
    		err = regulator_enable(vdd_lcd_bl_en);
    		if (err < 0) {
    			pr_err("vdd_lcd_bl_en regulator enable failed\n");
    			goto fail;
    		}
    	}
    
    	msleep(20);
    #if DSI_PANEL_RESET
    	/* use platform data */
    	gpio_direction_output(en_panel_rst, 1);
    	usleep_range(1000, 5000);
    	gpio_set_value(en_panel_rst, 0);
    	usleep_range(1000, 5000);
    	gpio_set_value(en_panel_rst, 1);
    	msleep(20);
    #endif
    
    	return 0;
    fail:
    	return err;
    }
    
    static int dsi_s_wqxga_10_1_enable(struct device *dev)
    {
    	return 0;
    }
    
    static int dsi_s_wqxga_10_1_disable(struct device *dev)
    {
    	if (vdd_lcd_bl)
    		regulator_disable(vdd_lcd_bl);
    
    	if (vdd_lcd_bl_en)
    		regulator_disable(vdd_lcd_bl_en);
    
    	if (avdd_lcd_3v3)
    		regulator_disable(avdd_lcd_3v3);
    
    	if (dvdd_lcd_1v8)
    		regulator_disable(dvdd_lcd_1v8);
    
    	return 0;
    }
    
    static int dsi_s_wqxga_10_1_postsuspend(void)
    {
    	return 0;
    }
    
    static int dsi_s_wqxga_10_1_bl_notify(struct device *dev, int brightness)
    {
    	struct backlight_device *bl = NULL;
    	struct pwm_bl_data *pb = NULL;
    	int cur_sd_brightness = atomic_read(&sd_brightness);
    	bl = (struct backlight_device *)dev_get_drvdata(dev);
    	pb = (struct pwm_bl_data *)dev_get_drvdata(&bl->dev);
    
    	/* SD brightness is a percentage */
    	brightness = (brightness * cur_sd_brightness) / 255;
    
    	/* Apply any backlight response curve */
    	if (brightness > 255)
    		pr_info("Error: Brightness > 255!\n");
    	else if (pb->bl_measured)
    		brightness = pb->bl_measured[brightness];
    
    	return brightness;
    }
    
    static int dsi_s_wqxga_10_1_check_fb(struct device *dev, struct fb_info *info)
    {
    	struct platform_device *pdev = NULL;
    	pdev = to_platform_device(bus_find_device_by_name(
    		&platform_bus_type, NULL, "tegradc.0"));
    	return info->device == &pdev->dev;
    }
    
    static struct pwm_bl_data_dt_ops  dsi_s_wqxga_10_1_pwm_bl_ops = {
    	.notify = dsi_s_wqxga_10_1_bl_notify,
    	.check_fb = dsi_s_wqxga_10_1_check_fb,
    	.blnode_compatible = "s,wqxga-10-1-bl",
    };
    
    struct tegra_panel_ops dsi_s_wqxga_10_1_ops = {
    	.enable = dsi_s_wqxga_10_1_enable,
    	.disable = dsi_s_wqxga_10_1_disable,
    	.postpoweron = dsi_s_wqxga_10_1_postpoweron,
    	.postsuspend = dsi_s_wqxga_10_1_postsuspend,
    	.pwm_bl_ops = &dsi_s_wqxga_10_1_pwm_bl_ops,
    };