Hi dimtass,
I show this information
ubuntu@tegra-ubuntu:~$ xrandr
Screen 0: minimum 8 x 8, current 720 x 576, maximum 16384 x 16384
DSI-0 connected (normal left inverted right x axis y axis)
720x576 50.00 +
HDMI-0 connected primary 720x576+0+0 (normal left inverted right x axis y axis) 0mm x 0mm
720x576 50.00*+
When I dual screen display or only DSI display, the output is black.why?
How to configure this place?
nvidia,dsi-init-cmd =
/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
/* For DSI packets each DT cell is interpreted as u8 not u32 */
<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0x10 0x00 0x2A 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0x10 0x01 0x01 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_TEARING_EFFECT_ON 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 120>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>;
nvidia,dsi-n-init-cmd = <14>;
nvidia,dsi-suspend-cmd =
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 50>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 200>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_TEARING_EFFECT_OFF 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>;
nvidia,dsi-n-suspend-cmd = <6>;
This is the print message. How to modify dsi clk. parent:81000000 will lead to errors " dsi: Tlpx mipi range violated" and “dsi: mipi range violated”
[ 2.132166] tegradc tegradc.0: DSI: HS clock rate is 81000
[ 2.139054] tegradc tegradc.0: nominal-pclk:27000000 parent:27000000 div:1.0 pclk:27000000 26730000~29430000
[ 2.211637] tegra_mipi_cal 700e3000.mipical: Mipi cal timeout,val:40013980, lanes:c0000000
[ 2.217910] tegra_mipi_cal 700e3000.mipical: MIPI_CAL_CTRL 0x00 0x2a000000
[ 2.226255] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS 0x08 0x40013980
[ 2.234557] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS_2 0x0c 0x00000020
[ 2.242888] tegra_mipi_cal 700e3000.mipical: CILA_MIPI_CAL_CONFIG 0x14 0x00000000
[ 2.251185] tegra_mipi_cal 700e3000.mipical: CILB_MIPI_CAL_CONFIG 0x18 0x00000000
[ 2.259515] tegra_mipi_cal 700e3000.mipical: CILC_MIPI_CAL_CONFIG 0x1c 0x00000000
[ 2.267847] tegra_mipi_cal 700e3000.mipical: CILD_MIPI_CAL_CONFIG 0x20 0x00000000
[ 2.276156] tegra_mipi_cal 700e3000.mipical: CILE_MIPI_CAL_CONFIG 0x24 0x00000000
[ 2.284495] tegra_mipi_cal 700e3000.mipical: CILF_MIPI_CAL_CONFIG 0x28 0x00000000
[ 2.292796] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG 0x38 0x00000000
[ 2.301105] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG 0x3c 0x00000000
[ 2.309448] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG 0x40 0x00200200
[ 2.317756] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG 0x44 0x00000200
[ 2.326088] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG0 0x58 0x00000000
[ 2.334396] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG1 0x5c 0x00000300
[ 2.342728] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG2 0x60 0x00010010
[ 2.351024] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG_2 0x64 0x00000000
[ 2.359354] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG_2 0x68 0x00000000
[ 2.367687] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG_2 0x70 0x00200002
[ 2.375998] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG_2 0x74 0x00000002
[ 2.978376] tegradc tegradc.0: dsi: Tlpx mipi range violated
[ 2.982053] tegradc tegradc.0: dsi: mipi range violated
[ 2.987359] tegradc tegradc.0: probed
[ 3.071335] tegradc tegradc.0: nominal-pclk:27000000 parent:81000000 div:3.0 pclk:27000000 26730000~29430000