Pixel clock is a common term in video that describes the constant rate at which pixels must flow so you get an entire frame of pixels in one refresh cycle. It’s also an easy way to understand the capability of a given video chip.
For example I need to transmit 2 streams one on each DSI interface. My resolution is 1920 x 1200 pixels at 24bpp. When you add in blanking that brings me to 2080 x 1249. My refresh rate is 60Hz (actually more accurately 59.87). So my pixel clock requirement would be 2080 * 1249 * 59.87 which is approximately 155.5MHz. So in order to keep up with my display I must deliver 24bits every 155.5Mhz which is approximately equal to 3.73Gbps.
This should run over the 6Gbps (4 lanes x 1.5Gbps) link but it is not clear to me from the documentation if the rest of the video pipeline can keep up with the full data rate or not. It’s also not clear to me if there might be some other limitation on maximum resolution or pixel clock for a single four lane DSI interface. In my case I need to run two 3.73Gbps streams, one on each DSI interface.
The “3480 x 1920 60Hz at 24bpp” comes from the “NVIDIA Tegra X1 Mobile Processor Technical Reference Manual” page 2144 Chapter 26: Display Interfaces: MIPI-DSI. Under features they show:
Maximum Video Mode resolution is
- Uncompressed: 3480x1920, 60 fps at 24 bpp
- Compressed: 4096x2304, 60 fps with 3:1 compression (8 bpp)
That appears to be in ganged mode so before I invest a lot of time and money into making some boards I wanted to check what the maximum resolution and pixel clock were for a single four lane DSI interface. Also I wanted to make sure there were not some other gotchas I didn’t understand.