DSI PADCTL Registers access has no effect

hi,
we have a custom board with a working DSI output at 16bit and 18bit but the 24bit refuses to output video.
First we assume that we have board layout issues and thus we’d like to try and manipulate the NVidia registers for A Lanes (TRM sections 24.16.6-24.16.16).
The first register DSI_PADCTL_A_LANES_PWR_DOWN_0 actually turns on and off the channel while other registers do not have effect:

  • PULL_DOWN
  • PRE_EMPHASIS
  • CPHY_MID_STRENGTH
  • LP_DRVR_IMPEDANCE_CTRL
  • LP_DRVR_SLEW_RATE_CTRL
    We have connected a differential probe to the A lane and see no effect on the signal.

Please advise.

Hi,

  1. Is there any error from dmesg when you try to output 24bit output? Also, what was your method to output 16 bit result on DSI?

  2. What is your method to write register? Do you use devmem tool?

  1. Is there any error from dmesg when you try to output 24bit output? Also, what was your method to output 16 bit result on DSI?
    No Error. What do you mean by method?

  2. What is your method to write register? Do you use devmem tool?
    devmem not devmem2

What files do you modify to let tegra output 24/18/16 bit data to your panel?

hi,

{
host1x {
dsi{
status = “okay”;
compatible = “nvidia,tegra186-dsi”;
panel-r-fpga-8-0_ch1 {
status = “okay”;
compatible = “r,fpga-8-0”;
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <2>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_16BIT_P>; //18BIT or 24BIT
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;//<TEGRA_DSI_VIDEO_CLOCK_TX_ONLY>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END>;

Just in case, could you still share the dmesg when you hit the error?

hi,

I’ve attached dmesg and scope image of the DSI signal.dmesg.txt (89.3 KB)

Could you also share the register value and command you are using?

Are you using jetpack3.x?

DSI_PADCTL_A_LANES_PWR_DOWN_0
sudo /bin/busybox devmem 0x15880014 32 0x7
sudo /bin/busybox devmem 0x15880014 32 0x0

DSI_PADCTL_A_PULL_DOWN_0
sudo /bin/busybox devmem 0x15880018 32 0x7
sudo /bin/busybox devmem 0x15880018 32 0x0

DSI_PADCTL_A_LP_DRVR_IMPEDANCE_CTRL_0
sudo /bin/busybox devmem 0x15880030 32 0x111111
sudo /bin/busybox devmem 0x15880030 32 0x333333
sudo /bin/busybox devmem 0x15880030 32 0x0

We use Jetpack 28.3

Hi,

What if you directly call the tegra_dsi_padctrl_shutdown function in your dsi driver? Will you see signal goes down in scope?

Hi,
why should I call the shut down function, this is the only register that actually works. What do you to achive with this testing?

Oh sorry. I missed comment #1.

So only DSI_PADCTL_A_LANES_PWR_DOWN_0 is working. Other functions don’t, right?

Maybe they work, though I see no effect on the DSI output signal.

Are the values correctly written into the register? Did you read them back?

Yes I’ve read them back to validate correctness.

1 Like

We will check this internally with our hardware guys. Please expect some delays.

Hi @igal.kroyter,

Do you have any idea what impact will you see from these registers?

Take DSI_PADCTL_A_PULL_DOWN_0 for example,

sudo /bin/busybox devmem 0x15880018 32 0x7
sudo /bin/busybox devmem 0x15880018 32 0x0

This register is useful during DSI link power-down or deep sleep mode. This is to ensure that lanes are pulled-down to zero when pad internal drivers are turned-off.

Thus, this register may have nothing to do with your 24bpp configuration.
If 24-bpp mode is not working, that means, it has something to do with DSI core configuration registers settings or Clock settings.

Hi, @WayneWWW,

Regarding DSI_PADCTL_A_PULL_DOWN_0 - got it.

what about DSI_PADCTL_A_LP_DRVR_IMPEDANCE_CTRL_0 or other registers that affect the slew rate? In other words, does the Parker have a register that can affect the signal of the DSI?

regarding the clock, one can see in the dmesg that the clock was almost doubled “tegradc 15200000.nvdisplay: DSI: HS clock rate is 445000” when the 24bit was set (from approx 189000).

Please advise.