Could you dump the clock tree when error happens?
sudo -s
/sys/kernel/debug/clk# cat clk_summary
And is the clock rate gives you the correct value when you set 16/18 bpp?
hi, @WayneWWW
the clock summary is attached.clk summary.txt (34.0 KB)
The clock from 16/18 bits is correct.
Could you also share us the full dts file? I just notice you didn’t paste it before.
Hi,
Why do you move the parent clock to pll_d3? Generally we use the pll_d for dsi.
Hi,
Generally, not intentinoally, I guess it was of my tries to fix the problem, and when I tried the 16/18 bits back it was wroking so I left it there.
Specifically, where this change was applied?
I guess your change to pll_d3 does not take effect. You clk tree shows the dsi is still under pll_d.
The difference between 24/18/16 bpp should be only in this part.
->tegra_dsi_init_config_param.
Could you check if number here is correct?
hi,
I have verified and added a print out of dsi->info.pixel_format parameter and I got 3 (TEGRA_DSI_PIXEL_FORMAT_24BIT_P). log is attached. Moreover, as I wrote before the clock is changing to the clock 445000000[Hz].termlog[07_32_41][04_01_2021].txt (76.7 KB)
Are you able to find out what variables decide this 445Mhz on your side?
I have added some prints out in tegra_dsi_init_clock_param which calculate and print out the DSI related clocks (look for DSI:). termlog[23_04_56][04_01_2021].txt (90.7 KB)
Could you also check the value when bpp is set to 18/16? Why is the value correct at that time and not correct when bpp is 24?
You should at least find some values match. For example, the pixel_clk_hz does not count the bpp so 18/16/24 should be same in this part.
Then, byte_clk_hz and plld_clk_mhz should decide the hs/lp clock. If you think they are wrong, could you point out which calculation is wrong?
I never said that the clocks are wrong, all I said was that our PCB layout does not provide the correct impedance for the DSI lines when higher frequencies are involved (as with the 24bits). As the name of the issue states I couold not see any effect when I access the DSI PADCTL registers.
Ok. Sorry that I misunderstood your comment here.
Hi,
Per checked with other engineers, we need these info for this issue
if 16-bit and 18-bit works fine, the padctl settings are fine and the same settings should even work 24-bit. Thus, we need the register dump from dsi. Please check /sys/kernel/debug/tegra_dsi and dump the reg.
Hi,
could you please advise how to dump the registers from /sys/kernel/debug/tegra_dsi?
just cat the node named reg under that path.
Also want to confirm… is this result based on the 24bpp config?
yes it is for 24bpp