DSI Video Output, Clock frequency control.

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

We are trying to use the DSI output through a fpga to drive a monitor.

We’ve got the DSI output signal looking roughly correct, but the frequency is wrong.

For the DSI converter that the TX2 DSI connects to it supports RGB 8:8:8 (24 bits) with DPHY clock expected as 445.5Mhz based on the below calculation

(148.5Mhz (pixel clock for 1080p 60) * 24bits (RGB 888)) / 4 data DSI channels = 891Mhz DSI data rate / 2 = 445.5 Mhz DPHY clock frequency

However, when I measure the clock frequency on DSI0_CLK+ and DSI0_CLK- the clock frequency on scope shows period of 4.480ns (223Mhz) regardless of the setting of the “clock-frequency” setting

How is the “clock-frequency” value convert to the DSI clock frequency on the TX2 ? Also what is the pixel data type configure for the DSI? RGB888 or RAW?

The Device Tree entries for the dsi are as follows:

dsi {
                status = "ok";
                panel-s-wqxga-10-1 {
                    status = "ok";
                    nvidia,dsi-video-data-type = <0x0>; /* VIDEO_MODE (not COMMAND_MODE) */
                    nvidia,dsi-video-clock-mode = <0x0>; /* CLOCK MODE CONTINUOUS */
                    /* nvidia,dsi-video-burst-mode = <0x3>;  TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED */
                    /* nvidia,dsi-video-burst-mode = <0x0>;  TEGRA_DSI_VIDEO_NONE */
                    nvidia,dsi-video-burst-mode = <0x1>; /* TEGRA_DSI_VIDEO_NONE_WITH_SYNC_END */
                    nvidia,dsi-power-saving-suspend = <0x0>;

                    disp-default-out {
                        nvidia,out-type = <0x2>;
                        nvidia,out-width = <0xd8>;
                        nvidia,out-height = <0x87>;
                        nvidia,out-flags = <0x00>; /* Continious Mode?? (was 0x20 one shot LP Mode) */
                        nvidia,out-parent-clk = "pll_d";
                        nvidia,out-xres = <1920>;
                        nvidia,out-yres = <1080>;
                        nvidia,out-rotation = <0>;
                    };
                    display-timings {

                        1920x1080-32 {
                            clock-frequency = <162000000>;
                            hactive = <1920>;
                            vactive = <1080>;
                            hfront-porch = <88>;
                            hback-porch = <148>;
                            hsync-len = <44>;
                            vfront-porch = <4>;
                            vback-porch = <36>;
                            vsync-len = <5>;
                            nvidia,h-ref-to-sync = <1>;
                            nvidia,v-ref-to-sync = <1>;
                        };

                        /delete-node/ 2560x1600-32;
                    };
                };
            };

Any insight would be helpful.

Thanks,

Cary

2

Could you dump the value in /sys/kernel/debug/clk/clk_summary? dsi clock should be under pll_d.

3

We get the following value for pll_d

clock enable_cnt prepare_cnt rate req_rate accuracy phase
pll_d 4 4 451997812 451998000 0 0

We are looking at the dsi-0_clk+ pin. (G33/G34)

We are reading 233 MHZ.

In the device tree we are setting 162 MHZ.

We are confused about how these relate to one an other.

Thanks,

Cary

4

As I understand, the clock frequency in device tree is the pixel clock.

if (!of_property_read_u32(np, "clock-frequency", &temp)) {
                    modes->pclk = temp;
                    OF_DC_LOG("of pclk %d\n", temp);

You can tracking the calculation in dsi.c, function: tegra_dsi_init_config_param

5

For the mode we are using, (CLOCK MODE CONTINUOUS) I do not believe this is the case.
The pixel clock (actually what we are measuring, i.e. the DSI PHY Clock) used seems to be calculated directly from frame rate, total lines, and total pixels (i.e. including blanking) in dsi.c tegra_dsi_init_clock_param(). The value read from the device tree seems (?) to be overwritten
in tegra_dsi_set_dsi_clk(). It’s all rather confusing.

We have been able to get a single DSI output to run through the DSI → Digital → HDMI conversion
hardware, we are now trying to get to two HDMI outputs running using the ganged left right
mode. There are still timing problems we are trying to work out.