dts file organization

I made a prototype carrier board and was able to do a full functional test by modifying various .dts and .dtsi files to make different component function one at a time. I never was able to change all of the carrier board functionality with a single .dtb.

I went ahead with the production run of carrier boards, but in the meantime, I need to iron out my device tree.

So, what I have is a p3489 (tx2i) sitting on something based on the p2597 carrier board.

USB 3.0 pd should be on all the time. It’s a hub.
SPI buses need to be enabled.
2 x PCIe pd needs to be on all the time.
The 4x PCIe is a x1.

Wich files do I need to modify to make the p2597 overlays my own?

Thanks!!

For the USB/PCIe, please refer to the TX2 adaptation guide.
I think there are still somehthing need to clarify.

What is the USB3.0 pd and 2xPCIe pd here? Where do you put them on the p2597 carrier board?
Why do you need to configure PCIe x4 port to x1? x1 devices should work fine even when connected to x4 port.

For the SPI,

https://elinux.org/Jetson/TX2_SPI

Does any know where the edits specific to the p2597 have been made in the device tree sources?

Isn’t there a better way than to extract a working device tree and modify it?

Even if you know where to modify device tree, you still need to find out what to modify and it depends on your usecase.
We cannot answer your question unless we know what you are doing. Please answer #2 first. Thanks.

The USB is the removal of the vbus detect from the i2c controller of the dev kit. Mine is a hub.

The PCIe is the removal of the M.2 clockdetect.

The x4 PCIe is fine, but I assumed it was 1 line in the dots for the controller

Are you using the release from jetpack3.3 or jetpack4.2?

I have been using the pre Xavier version. It’s 3.3

BConklin,

We think you could follow up the TX2 OEM design guide first and tell us what is your usb design.
Your so-called “always-on” should be “always as host mode”, right?

Also, you could see there is a table for configuring the USB/PCIe lane mapping. On tegra, pcie and usb3.0 are sharing the same lane and the functionality is switched between one of them.

There is no default x2 PCIe configuration, you may need to change it to config 5 or config 6. Please refer to TX2 adaptation guide for more detail.

Some practical example for how to change usb lane mapping

https://elinux.org/Jetson/TX2_USB

OK
This one worked.
The phandle for &vdd_usb0_5v turns out to be 0x19 if you want to just to it on the module. That detail is missing from the instructions at https://elinux.org/Jetson/TX2_USB

One down!

    pinctrl@3520000 {
            reg = <0x0 0x3520000 0x0 0x1000 0x0 0x3540000 0x0 0x1000>;
            interrupts = <0x0 0xa7 0x4>;
            vbus-2-supply = <0x19>;
            pinctrl-0 = <0x9c>;
            pinctrl-1 = <0x9d>;

Rather than try to find the PCIe clock enable for the TX2 carrier board in the dts files, it was easier to wire it one the carrier board to match the dev kit. No one seems to know where that is located.

Now I need to add the SPI.

Does anyone know where this section is the the dts files that apply to MY board?
Can I put it at the top level to overwrite anything else?

spi@3240000{
compatible = “nvidia,tegra186-spi”;
reg = <0x0 0x3240000 0x0 0x10000>;



linux,phandle = <0x80>;
spi@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = <0x1312D00>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delau = <0x0>;
};
};

FYI

https://elinux.org/Jetson/TX2_SPI

That’s where I got the dts code from above. The problem is that all of these articles tell you how to modify the target, and not the host. I wound up guessing what file to place the code into, and then checking to see if it made it’s way onto my target board. It seems that this is the only way, since no one knows what dts(i) files go into the jetson tx2i dev kit.

That’s where I got the dts code from above. The problem is that all of these articles tell you how to modify the target, and not the host. I wound up guessing what file to place the code into, and then checking to see if it made it’s way onto my target board. It seems that this is the only way, since no one knows what dts(i) files go into the jetson tx2i dev kit.

BConklin,

I think it is not hard to find out which file you should modify.If you want to make sure you change the dts file, just put it to the one you flash into device.

That is the “tegra186-quill-p3489-1000-a00-00-ucm1.dts”.

To check the runtime device tree, you could check the nodes under /proc/device-tree/ on your device.

Please note the even bootloader has chance to change the device tree, so it would be better to always check the runtime DT.