DTSI file to change in order to enable PEX1 instead od USB_SS)

Nvidia document describes to change a file to enable mux for PEX1 PHY instead of usb_ss0, but which file though?

To switch USB_SS0 to PEX1, configure QSPI_IO2 as follows:
pcie0_lane2_mux {
gpios = <TEGRA_MAIN_GPIO(R, 3) 0>;
label = “pcie-lane2-mux”;

  • status = “disabled”;
  • status = “okay”;

The TX2 files are


Done “pcie0_lane2_mux” set to “okay” and disabled xhci@3530000. So sees no usb-c activities when plugged usb-c client.
Modified p27771-0000.conf.common to have ODMDATA = 0x90000 with p3849 package.
pci@1,0 set to 4 lanes, pci@2,0 disabled, pci@3,0 set to 1 lane.
Still see no Serdes activities on PEX1 and lspci sees no port2? what to do/check next?
devmem 0x02520284
0x00000200 <------- wrong !!!
Somewhere still not connecting.

Please share which pins are used in the type C port for reference. On TX2 devkit, we don’t have type C port. We have it on Xavier devkit and you may refer to it for hardware design.

After I’ve modified p27771-0000.conf.common, is it enough just to compile kernel and flash it?

file modifications are here:
ODMDATA=0x90000; # default = C0X

elif [ "${bid}" \= "3489" ]; then

On page 14 of platform adaptation and bring-up guide, all usb3.0 OTG are "disabled’. Still UPHY lane0 comes back as 0x200 value.
Though all usb allocation is disabled for lane0, how do we setup lane0 is for pcie?


Please check the device tree on your board under node /proc/device-tree.
This is the real device tree that is read and run by the device.

Please check if all those nodes you’ve modified really meets your expectation.

In one of setup post of pcie config #1 was a good pointer:

But current DTS code has ‘DT_VERSION_2’ thrown into play, what to do?

xhci@3530000 {
	phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
	phy-names = "usb2-0", "usb2-1", "usb3-0";
	status = "okay";


xhci@3530000 {
status = “okay”;
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
phy-names = “utmi-0”, “utmi-1”, “usb3-0”;
nvidia,boost_cpu_freq = <800>;


Looks like the design is same as TX2 devkit. The USB3 Type-A port is USB3 C43 C44 F43 F44 + USB2 A38 A39 + VBUS A18. You don’t need to modify pcie0_lane2_mux. So the issue is about G42 G43 D42 D43 pins?

For information, do you use r32 release or r28 release? Adaptation guide 1.9 is for r32 and 1.7 is for r28.

After adding ODMDATA = “0x90000” to conf/local.conf + pcie0_lane2_mux change. PEX1 is working with Intel NIC recognized.
I agree with you that pcie0_lane2_mux is inconsequential, for plugging usb-c kernel reacts to it as well.
The doc I used is DA_08477-001, june 2018, bit older than you pointed to.