Effect of BG_VREF_LEVEL and BG_TEMP_COEF registers

Autonomous Machines Jetson & Embedded Systems Jetson TK1
1

Hello,

We would like to reduce LVDS bandgap output voltage from 0.7V to 0.6V.
According to datasheet, NV_SOR_PLL3.BG_VREF_LEVEL should be set to 0x01. But after measuring with oscilloscope, it remains at 0.7V.
Is there another register to configure to set voltage to 0.6V?

We noticed that when BG_TEMP_COEF is also set to 0 (NV_SOR_PLL3 = 0x00000220), then voltage has expected value of 0.6V.
Do you know what is the specification for BG_TEMP_COEF? (it is not documented in datasheet.)

Thanks for any information or pointers

2

BG_TEMP_COEF is Control bits for the bandgap’s temperature coeffcient .

please download the TK1 Technical Reference Manual for reference https://developer.nvidia.com/embedded/dlc/TK1-TRM

3

Thanks

I have already downloaded the reference manual. But there is no explanation on how to set the control bits and how it impacts the voltage. There is only a single line page 1881 :

“BG_TEMP_COEF : Control bits for the bandgap’s temperature coefficient”

4

hello karim.ammouche,

you could use the 3rdparty tools to control the register.
for example,

$ sudo devmem2

Usage:  devmem2 { address } [ type [ data ] ]
        address : memory address to act upon
        type    : access operation type : [b]yte, [h]alfword, [w]ord
        data    : data to be written

you may check [System Address Map] and calculate the register address by offset values.
thanks

5

Hello,

It is the tool I used to modify the register, using command:

devmem2 0x54540068 w 0x30000220

(NV_SOR_PLL3 address is 0x54540068)

It did not cause voltage level to drop to 0.6V as specified in datasheet.
To obtain 0.6V, we had to set BG_TEMP_COEF to 0.

The problem is that we are not sure the fix is correct. We would like to understand how BG_TEMP_COEF works to be sure it is the correct value. It is not described in datasheet.

Thanks

6

@karim.ammouche
Checked with internal, NV don’t suggest to change the BG_VREF_LEVEL and BG_TEMP_COEFF register.
Why do you want to tune BG_VREF_LEVEL register ?
if you want to lower output voltage swing for lower current consumption, please can tune below two register,
SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0, SOR_NV_PDISP_SOR_DP_PADCTL0_ TX_PU_VALUE

7

Hi Rita,

Thanks for the information.
The goal is to reduce LVDS bandgap voltage in order to be compliant with an LCD that requires 0.6V.
Power consumption is not the issue.

Thanks

8

@karim.ammouche
where are you probe when you measure the 0.6v or 0.7v? is the LVDS mode is use on your case ?
i still confuse why do you adjust the LVDS Bandgap voltage to meet LCD 0.6V ? do you explain the more detail? if do you want to tune the LVDS-COMMAND MODE Voltage but you adjust the Bandgap Voltage?