Enable Dual-core Lock Step for ARM CPU on Orin chips

Hi, as Orin is using ARM A78AE CPUs, which allow users to configure two cpus into one lock core to enable soft error prevention. I’m wondering how should that be activated? According to ARM documentation, this should be activated during boot time. But I haven’t read anything about it in Orin’s documentation in the boot section. Can someone help on this?

Best, Yiming.

To set the CEMODE, in the tegra234-mb1-bct-misc-common.dtsi file, you need to set the required value in the num_clusters_2core_pair_lockstep field, and complete the boot.

Refer to the Arm Cortex-A78AE Core Technical Reference Manual for the CEMODE values of the different execution modes.

… note::

  • Booting the standard/default Jetson Linux in lock/hybrid mode is not supported.

  • To boot in to the lock/hybrid mode, disable the C7 cpuidle state by setting the min-residency-us property to 0xFFFFFFFF in the following DT node:

    … code-block:: none

    cpu_core_power_states {
    c7 {

    min-residency-us = <30000>;
    status = “okay”;

Above will be available in the adaptation guide in next release

Thanks for the reply. Can I ask one further step? As I’m aware of, this tegra234-mb1-bct-misc-common.dtsi is in the L4T bootloader folder. As I have run through the ubuntu setup with oem-config (Getting Started with Jetson AGX Orin Developer Kit | NVIDIA Developer), does that mean I need to flash the system to L4T?

And if so, do we have any tutorial on how to do that on orin chips?

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