Please refer to the instruction in Pinmux Changes for detailed steps to apply the change.
Pleas also share the result of the following commands on your board in both cases. (working with Jetson-IO, not working with setup through spreadsheet).
$ sudo busybox devmem 0x0243d040
$ sudo busybox devmem 0x0243d020
$ sudo busybox devmem 0x0243d058
$ sudo busybox devmem 0x0243d010
$ sudo busybox devmem 0x0243d050
Pinmux with spreadsheet:
$ sudo busybox devmem 0x0243d040 # 0x00001417
$ sudo busybox devmem 0x0243d020 # 0x00001417
$ sudo busybox devmem 0x0243d058 # 0x00001417
$ sudo busybox devmem 0x0243d010 # 0x0000141B
$ sudo busybox devmem 0x0243d050 # 0x0000141B
Pinmux with Jetson-IO:
$ sudo busybox devmem 0x0243d040 # 0x00001444
$ sudo busybox devmem 0x0243d020 # 0x00001444
$ sudo busybox devmem 0x0243d058 # 0x00001444
$ sudo busybox devmem 0x0243d010 # 0x00001448
$ sudo busybox devmem 0x0243d050 # 0x00001448
Please share the screenshot of the pinmux spreadsheet to share how you configure those pins.
It seems you don’t configure SPI1_* for SPI usage in “Customer Usage”. (i.e. they are still configured for GPIO usage)
Please also noted that Int PU/Int PD are only valid for Input.
For Output, please configure Drive 0/Drive 1 for default pin state.
Even changing the spreadsheet it still did not work. The loopback mode still got zeros in the receiver.
Here some updates:
Pinmux with the new spreadsheet:
$ sudo busybox devmem 0x0243d040 # 0x00001055
$ sudo busybox devmem 0x0243d020 # 0x00001055
$ sudo busybox devmem 0x0243d058 # 0x00001001
$ sudo busybox devmem 0x0243d010 # 0x00001001
$ sudo busybox devmem 0x0243d050 # 0x00001001
SPI with default pins
Pin 22 - Q.1
Pin 32 - BB.1
Result of $sudo cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinconf-groups:
20 (can1_en_pbb1):
pull=0
tristate=0
enable-input=0
io-reset=0
rcv-sel=0
io-hv=0
schmitt=0
pull-down-strength=0
pull-up-strength=0
drive-type=2
func=rsvd0
pad-power=0
59 (soc_gpio21_pq1):
pull=0
tristate=0
enable-input=0
open-drain=0
io-reset=0
rcv-sel=0
io-hv=0
schmitt=0
pull-down-strength=0
pull-up-strength=0
drive-type=0
func=rsvd0
pad-power=0
195 (spi1_cs0_pz6):
pull=0
tristate=0
enable-input=0
open-drain=0
io-reset=1
rcv-sel=1
io-hv=1
schmitt=1
pull-down-strength=0
pull-up-strength=0
drive-type=0
func=rsvd1
pad-power=0
197 (spi1_miso_pz4):
pull=1
tristate=1
enable-input=1
open-drain=0
io-reset=1
rcv-sel=1
io-hv=1
schmitt=1
pull-down-strength=0
pull-up-strength=0
drive-type=0
func=rsvd1
pad-power=0
201 (spi1_sck_pz3):
pull=1
tristate=1
enable-input=1
open-drain=0
io-reset=1
rcv-sel=1
io-hv=1
schmitt=1
pull-down-strength=0
pull-up-strength=0
drive-type=0
func=rsvd1
pad-power=0
203 (spi1_cs1_pz7):
pull=0
tristate=0
enable-input=0
open-drain=0
io-reset=1
rcv-sel=1
io-hv=1
schmitt=1
pull-down-strength=0
pull-up-strength=0
drive-type=0
func=rsvd1
pad-power=0
204 (spi1_mosi_pz5):
pull=0
tristate=0
enable-input=0
open-drain=0
io-reset=1
rcv-sel=1
io-hv=1
schmitt=1
pull-down-strength=0
pull-up-strength=0
drive-type=0
func=rsvd1
pad-power=0
Just a reminder the source of device tree is this:
tegra194-p2888-0001-p2822-0000-common.dtsi
spi@3210000 {
status = "okay";
spi-max-frequency = <33000000>;
num-cs = <2>;
cs-gpios = <TEGRA194_AON_GPIO(BB, 1) GPIO_ACTIVE_LOW>, <TEGRA194_MAIN_GPIO(Q, 1) GPIO_ACTIVE_LOW>;
spi@0 {
compatible = "tegra-spidev";
reg = <0x00>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x11>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x01>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x11>;
};
};
};
It seems not the expected result to me.
And you still not configuring SPI2 in Customer Usage.
Please refer to the following configuration.
I apologise. I thought you were referring to another column because I thought I had already configured that column from the start.
It did not work.
I tried to change the source device tree back to the original and also did not work (using the original CS pins). But when I run the Jetson IO it shows the box of the spi1 it is already enabled. However, it is fixed by unchecking the box, saving the settings, and then checking the box again (in the Jetson IO)."
Spreedsheet SPI1:
$ sudo busybox devmem 0x0243d040 # 0x00001000
$ sudo busybox devmem 0x0243d020 # 0x00001050
$ sudo busybox devmem 0x0243d058 # 0x00001000
$ sudo busybox devmem 0x0243d010 # 0x00001000
$ sudo busybox devmem 0x0243d050 # 0x00001000
ORIGINAL: tegra194-p2888-0001-p2822-0000-common.dtsi
spi@3210000 {
status = "okay";
spi@0 {
compatible = "tegra-spidev";
reg = <0x00>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x11>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x01>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x11>;
};
};
};
They are not the expected result that the pin is used as GPIO rather than SFIO.
Could you share the steps how you apply the change for pinmux?
Do you mean that SPI would not work before unchecking the box?
and SPI would work after you unchecking/checking the box and reboot the board?
After getting the 3 .dtsi files from the spreadsheet I copy them to:
$JETPACK_ROOT/Linux_for_Tegra/kernel/pinmux/t19x/
Then I run:
python pinmux-dts2cfg.py --pinmux addr_info.txt gpio_addr_info.txt por_val.txt --mandatory_pinmux_file mandatory_pinmux.txt tegra19x-jetson_agx_devkit-pinmux.dtsi tegra19x-jetson_agx_devkit-gpio-default.dtsi 1.0 > tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg
to generate the tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg file.
Afterwards, I copied the config file to:
$JETPACK_ROOT/Xavier/Linux_for_Tegra/bootloader/t186ref/BCT
And finnaly I flash the device by running: sudo ./flash.sh jetson-agx-xavier-devkit mmcblk0p1.
Exactly.
Could you also share the result of pinmux register before and after using Jetson-IO to get it work?
$ sudo busybox devmem 0x0243d040
$ sudo busybox devmem 0x0243d020
$ sudo busybox devmem 0x0243d058
$ sudo busybox devmem 0x0243d010
$ sudo busybox devmem 0x0243d050
$ sudo busybox devmem 0x0243d040 # 0x00001444
$ sudo busybox devmem 0x0243d020 # 0x00001444
$ sudo busybox devmem 0x0243d058 # 0x00001444
$ sudo busybox devmem 0x0243d010 # 0x00001448
$ sudo busybox devmem 0x0243d050 # 0x00001448
I want to check the result before and after.
I am sorry for not answering the last post.
After configure pinout with the spreadsheet:
$ sudo busybox devmem 0x0243d040 # 0x00001000
$ sudo busybox devmem 0x0243d020 # 0x00001050
$ sudo busybox devmem 0x0243d058 # 0x00001000
$ sudo busybox devmem 0x0243d010 # 0x00001000
$ sudo busybox devmem 0x0243d050 # 0x00001000
After unchecked the SPI in the Jetson-IO:
$ sudo busybox devmem 0x0243d040 # 0x00001417
$ sudo busybox devmem 0x0243d020 # 0x00001417
$ sudo busybox devmem 0x0243d058 # 0x00001417
$ sudo busybox devmem 0x0243d010 # 0x0000141B
$ sudo busybox devmem 0x0243d050 # 0x0000141B
After enabling SPI in the Jetson-IO:
$ sudo busybox devmem 0x0243d040 # 0x00001444
$ sudo busybox devmem 0x0243d020 # 0x00001444
$ sudo busybox devmem 0x0243d058 # 0x00001444
$ sudo busybox devmem 0x0243d010 # 0x00001448
$ sudo busybox devmem 0x0243d050 # 0x00001448
It seems the the pinmux not configured correctly.
Could you share the command and the result when you run to generate pinmux-dts2cfg.py?
Please also share the generated cfg file.
In the Linux host I go to the following directory: *$JETPACK_ROOT/Linux_for_Tegra/kernel/pinmux/t19x/
I paste the generated .dtsi files from the spreadsheet.
tegra19x-jetson_agx_xavier_devkit-gpio-default.dtsi
tegra19x-jetson_agx_xavier_devkit-padvoltage-default.dtsi
tegra19x-jetson_agx_xavier_devkit-pinmux.dtsi
Then I run the following command:
python pinmux-dts2cfg.py --pinmux addr_info.txt gpio_addr_info.txt por_val.txt --mandatory_pinmux_file mandatory_pinmux.txt tegra19x-jetson_agx_devkit-pinmux.dtsi tegra19x-jetson_agx_devkit-gpio-default.dtsi 1.0 > tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg
And got this result:
ERROR: pin dap1_sclk_ps0(0x00000440) field nvidia,enable-input(0x00000040) is not matching, val = 0x01 expected = 0x00
ERROR: pin dap1_fs_ps3(0x00000440) field nvidia,enable-input(0x00000040) is not matching, val = 0x01 expected = 0x00
ERROR: pin eqos_rd3_pf1(0x00022470) field nvidia,lpbk(0x00000020) is not matching, val = 0x01 expected = 0x00
ERROR: pin eqos_sma_mdio_pf4(0x00022440) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin sdmmc4_cmd(0x00002440) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin soc_gpio10_pg6(0x00000410) field nvidia,tristate(0x00000010) is not matching, val = 0x01 expected = 0x00
ERROR: pin soc_gpio13_ph1(0x00000411) field nvidia,tristate(0x00000010) is not matching, val = 0x01 expected = 0x00
ERROR: pin gp_pwm2_px2(0x00000410) field nvidia,tristate(0x00000010) is not matching, val = 0x01 expected = 0x00
ERROR: pin gp_pwm3_px3(0x00000410) field nvidia,tristate(0x00000010) is not matching, val = 0x01 expected = 0x00
ERROR: pin uart2_tx_px4(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart2_rts_px6(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart5_tx_py5(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart5_rts_py7(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart3_tx_pcc5(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin soc_gpio22_pq2(0x00000459) field nvidia,pull(0x0000000c) is not matching, val = 0x02 expected = 0x00
ERROR: pin uart1_tx_pr2(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin dap4_sclk_pa4(0x0000c440) field nvidia,enable-input(0x00000040) is not matching, val = 0x01 expected = 0x00
ERROR: pin dap4_fs_pa7(0x0000c440) field nvidia,enable-input(0x00000040) is not matching, val = 0x01 expected = 0x00
ERROR: pin ufs0_ref_clk_pff0(0x00022420) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x01
ERROR: pin ufs0_rst_pff1(0x00022420) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
The config file (tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg.txt (30.4 KB)):
#### Pinmux for gpio-input pins ####
pinmux.0x0243d040 = 0x00000000; # GPIO spi1_sck_pz3
pinmux.0x0243d020 = 0x00000000; # GPIO spi1_miso_pz4
pinmux.0x0243d058 = 0x00000000; # GPIO spi1_mosi_pz5
pinmux.0x0243d010 = 0x00000000; # GPIO spi1_cs0_pz6
pinmux.0x0243d050 = 0x00000000; # GPIO spi1_cs1_pz7
#### Pinmux for used pins ####
pinmux.0x0243d040 = 0x00001055; # spi1_sck_pz3: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d020 = 0x00001055; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00001055; # spi1_mosi_pz5: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00001059; # spi1_cs0_pz6: rsvd1, pull-up, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d050 = 0x00001059; # spi1_cs1_pz7: rsvd1, pull-up, tristate-enable, input-enable, lpdr-disable
Then I copy that config file to $JETPACK_ROOT/Linux_for_Tegra/bootloader/t186ref/BCT and flash the device.
Please remove --mandatory_pinmux_file mandatory_pinmux.txt when you are generating cfg and check if the error messages could be eliminated.
It’s not the expected result for SPI usage.
Let me share my result as following:
pinmux.0x0243d040 = 0x00001400; # spi1_sck_pz3: spi1, tristate-disable, input-disable, lpdr-disable
pinmux.0x0243d020 = 0x00001450; # spi1_miso_pz4: spi1, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00001400; # spi1_mosi_pz5: spi1, tristate-disable, input-disable, lpdr-disable
pinmux.0x0243d010 = 0x00001400; # spi1_cs0_pz6: spi1, tristate-disable, input-disable, lpdr-disable
pinmux.0x0243d050 = 0x00001400; # spi1_cs1_pz7: spi1, tristate-disable, input-disable, lpdr-disable
I could fix this issue by reinstalling the BSP package and downloading again the spreadsheet. With the addresses of the pinmux registers fixed the SPI finally works.
I configure the BB.01 pin and Q.01 pin as GPIO. During the steps of rebuilding the kernel I need to set 2 environment variables:
$ export CROSS_COMPILE_AARCH64_PATH=$HOME/l4t-gcc
$ export CROSS_COMPILE_AARCH64=$HOME/l4t-gcc/bin/aarch64-buildroot-linux-gnu-
And afterwards, I needed to run in the Linux_for_Tegra/sources/ the command:
$ sudo ./nvbuild.sh -o $PWD/kernel_out
But I got this error: Error: Env variable CROSS_COMPILE_AARCH64_PATH is not set!!
I previously had this error related to missing permissions, but I couldn’t solve it now.
I run all these steps in the same terminal and I can successfully use the “echo” command of the environment variables.
It seems your toolchain is not configured correctly.
Please use full path for CROSS_COMPILE_AARCH64 and CROSS_COMPILE_AARCH64_PATH. (i.e. instead of $HOME)
Unfortunately using the full path didn’t solve the issue.
EDIT1: This error doesn’t appear if I don’t use the sudo command. Therefore, an error appears that cannot open the ‘drivers/video/tegra/Kconfig’ file