Enable PCIe Controller C4 on Xavier

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Hi,

I want to enable PCIe controller C4 on Xavier in root-complex mode. Based on OEM and ODMDATA setting (pcie-xbar-4-1-0-1-2), C4 can only use 2 lanes: UPHY8 and UPHY9. However, C4 seems disabled in devkit.
My questions are:

  1. Can C4 be enabled in root-complex mode and using 2 lanes (UPHY8 and UPHY9)?
  2. If so, what need to do to enable C4? Just need to change Linux device-tree to enable C4 and set its uphy mapping properly? Do I need any change in BPMP-DTB or ODMDATA, or anything else?

Thanks.

3

  1. Yes. C4 can be enabled in root port mode but the devkit doesn’t have any PCIe slot that C4 controller can own. If you have a different carrier board which has a slot for C4 controller, by all means you can enable C4 and use that slot

  2. Just enable the C4 controller in the DT. The following patch can help you do that.

    diff --git a/common/tegra194-p2888-0000-a00.dtsi b/common/tegra194-p2888-0000-a00.dtsi
    index 2c5f7eb…4c01d89 100644
    — a/common/tegra194-p2888-0000-a00.dtsi
    +++ b/common/tegra194-p2888-0000-a00.dtsi
    @@ -133,6 +133,22 @@
    phy-names = “pcie-p2u-0”;
    };

    • pcie@14160000 {
    • status = “okay”;
    • vddio-pex-ctl-supply = <&p2888_spmic_sd3>;
    • nvidia,disable-aspm-states = <0xf>;
    • nvidia,enable-power-down;
    • nvidia,disable-clock-request;
    • nvidia,max-speed = <4>;
    • phys = <&p2u_8>,
    • <&p2u_9>;
    • phy-names = “pcie-p2u-0”, “pcie-p2u-1”;
    • };

    pcie@141a0000 {
    status = “disabled”;

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