Hi,
I’d like to be able to login to one of the TX1 serial consoles from my laptop using a USB-to-serial crossover cable. Currently, I’m using minicom as the tty client on my laptop, and the J21 UART pins on the TX1 as described here http://www.jetsonhacks.com/2015/12/01/serial-console-nvidia-jetson-tx1/. All of the bootconsole processes log in minicom, but communication between the two devices appears to cease after the bootconsole is disabled. I’d like to know what changes I need to make (use a different serial port, or enable the correct tty) so that I can login to the TX1 via serial connection after it boots.
When I boot the TX1, I get the following output in minicom
Welcome to minicom 2.7
OPTIONS: I18n
Compiled on Jan 1 2014, 17:13:19.
Port /dev/ttyUSB0, 11:37:58
Press CTRL-A Z for help on special keys
[0000.191] [TegraBoot] (version 24.00.2015.42-mobile-ec3b827e)
[0000.197] Processing in cold boot mode Bootloader 2
[0000.201] A02 Bootrom Patch rev = 63
[0000.205] Power-up reason: on button
[0000.208] No Battery Present
[0000.211] RamCode = 0
[0000.213] Platform has Ddr4 type ram
[0000.216] max77620 disabling SD1 Remote Sense
[0000.220] Setting Ddr voltage to 1125mv
[0000.224] Serial Number of Pmic Max77663: 0x1401f4
[0000.232] Entering ramdump check
[0000.235] Get RamDumpCarveOut = 0x0
[0000.238] RamDumpCarveOut=0x0, RamDumperFlag=0xe59ff3f8
[0000.243] Last reboot was clean, booting normally!
[0000.248] Sdram initialization is successful
[0000.252] SecureOs Carveout Base=0xff800000 Size=0x00800000
[0000.258] GSC1 Carveout Base=0xff700000 Size=0x00100000
[0000.263] GSC2 Carveout Base=0xff600000 Size=0x00100000
[0000.268] GSC3 Carveout Base=0xff500000 Size=0x00100000
[0000.273] GSC4 Carveout Base=0xff400000 Size=0x00100000
[0000.278] GSC5 Carveout Base=0xff300000 Size=0x00100000
[0000.283] BpmpFw Carveout Base=0xff2c0000 Size=0x00040000
[0000.289] Lp0 Carveout Base=0xff2bf000 Size=0x00001000
[0000.304] RamDump Carveout Base=0xff23f000 Size=0x00080000
[0000.309] Platform-DebugCarveout: 0
[0000.313] Nck Carveout Base=0xff03f000 Size=0x00200000
[0000.318] Non secure mode. Disable rollback prevention
[0000.323] AOTAG Init Done
[0000.370] Using GPT Primary to query partitions
[0000.376] Loading Tboot-CPU binary
[0000.425] Verifying bootloader in OdmNonSecureSBK mode
[0000.435] Bootloader load address is 0xa0000000, entry address is 0xa0000258
[0000.442] Bootloader downloaded successfully.
[0000.446] Downloaded Tboot-CPU binary to 0xa0000258
[0000.451] MAX77620_GPIO1 Configured.
[0000.454] MAX77620_GPIO5 Configured.
[0000.458] CPU power rail is up
[0000.461] CPU clock enabled
[0000.464] Performing RAM repair
[0000.467] Updating A64 Warmreset Address to 0xa00002e9
[0000.484] Bootloader DTB Load Address: 0x83000000
[0000.501] Kernel DTB Load Address: 0x83080000
[0000.506] Loading cboot binary
[0000.600] Verifying bootloader in OdmNonSecureSBK mode
[0000.694] Bootloader load address is 0x8010fda8, entry address is 0x80110000
[0000.701] Bootloader downloaded successfully.
[0000.706] GPT: Partition NOT found !
[0000.709] Find Partition via GPT Failed
[0000.713] Find Partition via PT Failed
[0000.716] function NvTbootGetBinaryOffsets: 0x1 error
[0000.721] Error in NvTbootLoadBinary: 0x1 !
[0000.725] Next binary entry address: 0x80110000
[0000.729] BoardId: 2180
[0000.755] NvTbootI2cProbe(): error code 0x00045100 Error while read
[0000.761] Display board id is not available
[0000.766] dram memory type is 3
[0000.770] WB0 init successful
[0000.796] Bpmp FW successfully loaded
[0000.799] Set NvDecSticky Bits
[0000.803] GSC1 address : ff700000
[0000.806] GSC2 address ff63fffc value c0edbbcc
[0000.811] GSC2 address : ff600000
[0000.814] GSC3 address : ff500000
[0000.818] GSC4 address : ff400000
[0000.822] GSC5 address : ff300000
[0000.825] GSC MC Settings done
[0000.829] TOS old plaintext Image length 65536
[0000.835] *** Secure OS image signature not verified ***
[0000.840] Loading and Validation of Secure OS Successful
[0000.845] NvTbootPackSdramParams: start.
[0000.850] NvTbootPackSdramParams: done.
[0000.854] Tegraboot started after 171284 us
[0000.858] Basic modules init took 312952 us
[0000.862] Sec Bootdevice Read Time = 194 ms, Read Size = 8464 KB
[0000.868] Sec Bootdevice Write Time = -1940251267 ms, Write Size = 343597383 KB
[0000.875] Next stage binary read took 12282 us
[0000.879] Carveout took 253090 us
[0000.882] CPU initialization took 125376 us
[0000.886] Total time taken by TegraBoot 703700 us
[0000.891] Starting CPU & Halting co-processor
64b[0000.999] RamCode = 0
[0001.014] LPDDR4 Training: Read DT: Number of tables = 10
[0001.019] EMC Training (SRC-freq: 204000; DST-freq: 40800)
[0001.024] EMC Training Skipped
[0001.027] EMC Training (SRC-freq: 204000; DST-freq: 68000)
[0001.032] EMC Training Skipped
[0001.035] EMC Training (SRC-freq: 204000; DST-freq: 102000)
[0001.040] EMC Training Skipped
[0001.043] EMC Training (SRC-freq: 204000; DST-freq: 204000)
[0001.048] EMC Training Skipped
[0001.051] EMC Training (SRC-freq: 204000; DST-freq: 408000)
[0001.057] EMC Training Successful
[0001.060] EMC Training (SRC-freq: 204000; DST-freq: 665600)
[0001.066] EMC Training Successful
[0001.069] EMC Training (SRC-freq: 204000; DST-freq: 800000)
[0001.080] EMC Training Successful
[0001.083] EMC Training (SRC-freq: 204000; DST-freq: 1065600)
[0001.106] EMC Training Successful
[0001.109] EMC Training (SRC-freq: 204000; DST-freq: 1331200)
[0001.131] EMC Training Successful
[0001.134] EMC Training (SRC-freq: 204000; DST-freq: 1600000)
[0001.153] EMC Training Successful
[0001.156] Switching to 800000 KHz Success
[0001.163] DT Write: emc-table@40800 succeeded
[0001.169] DT Write: emc-table@68000 succeeded
[0001.175] DT Write: emc-table@102000 succeeded
[0001.182] DT Write: emc-table@204000 succeeded
[0001.188] DT Write: emc-table@408000 succeeded
[0001.194] DT Write: emc-table@665600 succeeded
[0001.201] DT Write: emc-table@800000 succeeded
[0001.207] DT Write: emc-table@1065600 succeeded
[0001.213] DT Write: emc-table@1331200 succeeded
[0001.220] DT Write: emc-table@1600000 succeeded
[0001.224] LPDDR4 Training: Write DT: Number of tables = 10
U-Boot 2015.07-rc2-g78c8468 (Nov 09 2016 - 19:39:36 -0800)
TEGRA210
Model: NVIDIA P2371-2180
DRAM: 4 GiB
MC: Tegra SD/MMC: 0, Tegra SD/MMC: 1
*** Warning - bad CRC, using default environment
tegra-pcie: PCI regions:
tegra-pcie: I/O: 0x0000000012000000-0x0000000012010000
tegra-pcie: non-prefetchable memory: 0x0000000013000000-0x0000000020000000
tegra-pcie: prefetchable memory: 0x0000000020000000-0x0000000040000000
tegra-pcie: 4x1, 1x1 configuration
tegra-pcie: probing port 0, using 4 lanes
tegra-pcie: link 0 down, retrying
tegra-pcie: link 0 down, retrying
tegra-pcie: link 0 down, retrying
tegra-pcie: link 0 down, ignoring
tegra-pcie: probing port 1, using 1 lanes
tegra-pcie: link 1 down, retrying
tegra-pcie: link 1 down, retrying
tegra-pcie: link 1 down, retrying
tegra-pcie: link 1 down, ignoring
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0
MMC: no card present
switch to partitions #0, OK
mmc0(part 0) is current device
Scanning mmc 0:1...
Found /boot/extlinux/extlinux.conf
Retrieving file: /boot/extlinux/extlinux.conf
956 bytes read in 150 ms (5.9 KiB/s)
p2371-2180 eMMC boot options
1: primary kernel
Enter choice: 1: primary kernel
Retrieving file: /boot/initrd
6902654 bytes read in 325 ms (20.3 MiB/s)
Retrieving file: /boot/Image
20048144 bytes read in 501 ms (38.2 MiB/s)
append: fbcon=map:0 console=tty0n8 androidboot.modem=none androidboot.serialno=t
Retrieving file: /boot/tegra210-jetson-tx1-p2597-2180-a01-devkit.dtb
423986 bytes read in 456 ms (907.2 KiB/s)
## Flattened Device Tree blob at 82000000
Booting using the fdt blob at 0x82000000
reserving fdt memory region: addr=80000000 size=20000
Using Device Tree in place at 0000000082000000, end 000000008206a831
Starting kernel ...
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 3.10.96-tegra (buildbrain@mobile-u64-1072) (gcc ve6
[ 0.000000] CPU: Cortex A57 Processor [411fd071] revision 1
[ 0.000000] alternative: enabling workaround for ARM erratum 832075
[ 0.000000] Machine: jetson_tx1
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Reserved memory: initialized node iram-carveout, compatible id nt
[ 0.000000] Tegra reserved memory:
[ 0.000000] LP0: ff2bf000 - ff2bffff
[ 0.000000] Bootloader framebuffer: 00000000 - 00000000
[ 0.000000] Bootloader framebuffer2: 00000000 - 00000000
[ 0.000000] Framebuffer: 00000000 - 00000000
[ 0.000000] 2nd Framebuffer: 00000000 - 00000000
[ 0.000000] Carveout: 00000000 - 00000000
[ 0.000000] Vpr: 00000000 - 00000000
[ 0.000000] Tsec: 00000000 - 00000000
[ 0.000000] Bootloader Debug Data: 00000000 - 00000000
[ 0.000000] Nvdumper: ff23f000 - ff23ffff
[ 0.000000] cma: CMA: reserved 16 MiB at fdc00000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv0.2 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] DTS File Name: /dvs/git/dirty/git-master_linux/kernel/arch/arm64s
[ 0.000000] DTB Build time: Nov 9 2016 19:40:03
[ 0.000000] Tegra21: Speedo/IDDQ fuse revision 4
[ 0.000000] Tegra21: CPU Speedo ID 7, Soc Speedo ID 0, Gpu Speedo ID 2
[ 0.000000] Tegra21: CPU Process ID 0, Soc Process ID 1, Gpu Process ID 0
[ 0.000000] Tegra21: CPU Speedo value 2044, Soc Speedo value 1954, Gpu Speed5
[ 0.000000] Tegra21: CPU IDDQ 2136, Soc IDDQ 2336, Gpu IDDQ 2855
[ 0.000000] Tegra Revision: A02 SKU: 0x17 CPU Process: 0 Core Process: 1 Boof
[ 0.000000] tegra: PLLP fixed rate: 408000000
[ 0.000000] pll_u: boot with h/w control already set
[ 0.000000] pll_x boot misc1 0x0 : expected 0x20
[ 0.000000] (comparison mask = 0xffffff)
[ 0.000000] pll_c4 rates match 204000000 max sdmmc: vco=998400000 out0=998400
[ 0.000000] Lowering vic03 maximum rate from 1000000000 to 627200000
[ 0.000000] Lowering nvjpg maximum rate from 1000000000 to 627200000
[ 0.000000] Lowering se maximum rate from 1000000000 to 627200000
[ 0.000000] Lowering tsecb maximum rate from 1000000000 to 627200000
[ 0.000000] Lowering msenc maximum rate from 1000000000 to 716800000
[ 0.000000] Lowering nvdec maximum rate from 1000000000 to 716800000
[ 0.000000] Lowering vi maximum rate from 1000000000 to 793600000
[ 0.000000] Lowering isp maximum rate from 1000000000 to 793600000
[ 0.000000] Lowering adsp_bus maximum rate from 1200000000 to 844800000
[ 0.000000] Lowering sbus maximum rate from 600000000 to 408000000
[ 0.000000] Lowering host1x maximum rate from 600000000 to 408000000
[ 0.000000] Lowering pll_c maximum rate from 1200000000 to 1130000000
[ 0.000000] Lowering pll_c2 maximum rate from 1200000000 to 1130000000
[ 0.000000] Lowering pll_c3 maximum rate from 1200000000 to 1130000000
[ 0.000000] Lowering pll_d2 maximum rate from 1500000000 to 1130000000
[ 0.000000] Lowering pll_dp maximum rate from 1500000000 to 1130000000
[ 0.000000] Lowering sor0 maximum rate from 600000000 to 540000000
[ 0.000000] Lowering sor1 maximum rate from 600000000 to 594000000
[ 0.000000] Lowering dmic1 maximum rate from 12288000 to 12190000
[ 0.000000] Lowering dmic2 maximum rate from 12288000 to 12190000
[ 0.000000] Lowering dmic3 maximum rate from 12288000 to 12190000
[ 0.000000] Lowering hda maximum rate from 102000000 to 51000000
[ 0.000000] Lowering sdmmc2 maximum rate from 266000000 to 204000000
[ 0.000000] Lowering qspi maximum rate from 163200000 to 116600000
[ 0.000000] Lowering gbus maximum rate from 1300000000 to 998400000
[ 0.000000] Lowering cpu_g maximum rate from 3000000000 to 1734000000
[ 0.000000] Lowering cpu_lp maximum rate from 1350000000 to 1132800000
[ 0.000000] tegra dvfs: vdd_cpu: nominal 1226mV, offset 708000uV, step 19200d
[ 0.000000] tegra dvfs: vdd_core: nominal 1075mV, offset 0uV, step 12500uV, d
[ 0.000000] tegra dvfs: vdd_gpu: nominal 1110mV, offset 710000uV, step 10000d
[ 0.000000] Tegra reset control registration success
[ 0.000000] tegra_powergate_init: DONE
[ 0.000000] PERCPU: Embedded 13 pages/cpu @ffffffc01fecf000 s20800 r8192 d248
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pa2
[ 0.000000] Kernel command line: fbcon=map:0 console=tty0n8 androidboot.modet
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 byte)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] Memory: 2030MB 2048MB = 4078MB total
[ 0.000000] Memory: 4067000k/4067000k available, 108872k reserved
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 )
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc05400000 ( 56 )
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 )
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc100000000 ( 4096 )
[ 0.000000] .init : 0xffffffc00114f000 - 0xffffffc0011ba140 ( 429 )
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc00114e3a4 ( 17209 )
[ 0.000000] .data : 0xffffffc0011ce000 - 0xffffffc00139e7f0 ( 1858 )
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] NR_IRQS:704 nr_irqs:704 0
[ 0.000000] the number of interrupt controllers found is 6
[ 0.000000] Architected local timer running at 19.20MHz (phys).
[ 0.000000] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 3579s
[ 0.000000] Console: colour dummy device 80x25
[ 0.000000] console [tty0] enabled, bootconsole disabled
The TX1 does continue to boot normally, but no more output is logged to minicom. I’m a novice to embedded computing, so most of the above output means nothing to me. However, the fact that the output ends with the line
[ 0.000000] console [tty0] enabled, bootconsole disabled
suggests to me that I’m able to read the bootconsole via J21, but not any of the other consoles. Further running
dmesg | grep tty
on the TX1 gives
[ 0.000000] Kernel command line: fbcon=map:0 console=tty0n8 androidboot.modem=none androidboot.serialno=P2180A00P00940c003fd androidboot.security=non-secure tegraid=21.1.2.0.0 ddr_die=2048M@2048M ddr_die=2048M@4096M section=256M memtype=0 usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 debug_uartport=lsport,0 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff2bf000 nvdumper_reserved=0xff23f000 core_edp_mv=1125 core_edp_ma=4000 gpt android.kerneltype=normal androidboot.touch_vendor_id=0 androidboot.touch_panel_id=63 androidboot.touch_feature=0 androidboot.bootreason=pmc:software_reset,pmic:0x0 net.ifnames=0 root=/dev/mmcblk0p1 rw rootwait
[ 0.000000] console [tty0] enabled, bootconsole disabled
[ 1.135764] 70006000.serial: ttyS0 at MMIO 0x70006000 (irq = 68) is a Tegra
[ 1.136660] 70006040.serial: ttyTHS1 at MMIO 0x70006040 (irq = 69) is a SERIAL_TEGRA
[ 1.136959] 70006200.serial: ttyTHS2 at MMIO 0x70006200 (irq = 78) is a SERIAL_TEGRA
[ 1.137336] 70006300.serial: ttyTHS3 at MMIO 0x70006300 (irq = 122) is a SERIAL_TEGRA
To me this looks only the virtual console (tty0) is enabled. I’m unsure of what the lines that end with “is a Serial Tegra” mean, although I believe ttyTHS1 is the J21 serial console.
Any help with this would be greatly appreciated.