I think spi1 (ulpi_stp_py3) located at hardware PINs 4,5,6,7 on J3A1 as shown in the schematic corresponds to spi@7000d400, which is also used as SPI for touch screen configuration and but not spi@7000d600.
(TS_SPI_SCK → 4
TS_SPI_MOSI → 5
TS_SPI_CS_L → 6
TS_SPI_MISO → 7)
If it will help. I am running grinch 19.3 and the pin ulpi_stp_py3 in my dtsi file reads,
ulpi_stp_py3 {
nvidia,pins = "ulpi_stp_py3";
nvidia,function = "spi1";
nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
nvidia,tristate = <TEGRA_PIN_NORMAL>;
};
Anyone had success to enable cs-gpios for more SPI-Slaves? My current dts-File looks like that. I have access to /dev/spidev0.0 and /dev/spidev0.1 but for my second filedescriptor there is no chip-select signal on my configured GPIO pin (GPIO_PH1, pin 50 at J3A1)
/* Additionally enable spidev */
spi@0,7000d400 {
status = "okay";
cs-gpios = <0>, <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_LOW>;
num-chipselects = <2>;
spi0_0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "spidev";
reg = <0>;
spi-cpha;
spi-max-frequency = <5000000>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
spi0_1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "spidev";
reg = <1>;
spi-cpha;
spi-max-frequency = <5000000>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};