So I think I figured out most of my issue there was a tiny bug on my end. It wasn’t related to the pinmux.
I still have some questions about the UART table that you listed. I’ve been confused about the UART naming scheme for awhile, and I’ve gotten some conflicting info from NVIDIA documentation for the TX2. The Parker TRM seems to use the A-G naming scheme, but the OEM guide and the Dev Kit Spec use the numbering scheme and I they don’t seem to be 1-1 mapped. Can you confirm?
You seem to be implying that the mapping is:
UARTA -> UART0
UARTB -> UART1
UARTC -> UART2
The Dev Board Spec lists the pins on J17 as UART1, but these pins trigger the interrupt for UARTC.
Furthermore, the OEM guide Table 75 has this mess:
Module Pins (Tegra Functions) | I/O Block | Typical Usage
UART0 (UART1) | DEBUG | Debug
UART1 (UART3) | AO | Serial Port
UART2 (UART2) | UART | M.2 socket for external WLAN / BT
UART3 (UART4) | CONN | ...
UART7 (UART7) | AO | 2nd Debug/Misc.
Reading between the lines I think it means that UART0 = UARTA, UART1=UARTC, UART2=UARTB, UART3=UARTD, UART7=UARTG.
This seems to also align with the TRM’s table:
But the fact that there are three naming schemes, one with letters, one with zero-indexed numbers, and one with one-indexed numbers is a source of constant pain for me (especially because they don’t map as you might expect). This doesn’t even get into the Ball names, PADCTRL names, etc. Is there a definitive table or spreadsheet somewhere?