Enabling DMA for PCIe Transactions on AGX Xavier Industrial Board

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

Hi,

I am currently working on an AGX Xavier industrial custom board where we are utilizing the AGX Xavier board as the root complex and the Xilinx board as the endpoint for PCIe communication.

We are encountering delays in transferring bulk data from the endpoint to the root complex via PCIe. After some investigation, it seems that enabling Direct Memory Access (DMA) for PCIe transactions could significantly improve the data transfer speed and efficiency.

I kindly request your assistance in guiding us on how to enable DMA for PCIe transactions on our AGX Xavier board. If there are any specific configurations or settings that need to be adjusted, your insights would be invaluable. Additionally, if you have any example code or reference materials that demonstrate the implementation of PCIe DMA for data transfer, it would be greatly appreciated if you could share them with us.

To provide you with more context, here are some details about our endpoint configuration:

  1. Link Speed: 5.0 Gb/s
  2. Number of Lanes: x4

Thank you in advance for your support and assistance.

3

DMA engine is provided by the endpoint. So actually it needs the help from Xilinx.

5

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