Enabling More Verbose output For VI errors?

Hi There,
I’m wondering if it’s possible to enable more verbose output for VI errors on the Tegra?

We are trying to get new firmware settings for our custom cameras to work (the HW works with the previous settings), and are running into issues…

After starting streaming on the cameras, we see the following errors in the kernel log.

Jul 12 16:30:57 tegrax1 kernel: [ 3879.446424] vi vi: CSI 3 syncpt timeout, syncpt = 4, err = -11
Jul 12 16:30:57 tegrax1 kernel: [ 3879.452945] vi vi: TEGRA_CSI_CSI_CIL_STATUS 0x00000000
Jul 12 16:30:57 tegrax1 kernel: [ 3879.458783] vi vi: TEGRA_CSI_CSI_CILX_STATUS 0x00000000
Jul 12 16:30:57 tegrax1 kernel: [ 3879.464702] vi vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
Jul 12 16:30:57 tegrax1 kernel: [ 3879.470980] vi vi: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
Jul 12 16:30:59 tegrax1 kernel: [ 3881.446379] vi vi: MW_ACK_DONE syncpoint time out!

Unfortunately at the moment all error registers are 0, so there isn’t much info about what might be wrong beyond the general syncpoint error.

I haven’t tried changing the settle time value

cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_PHY_CONTROL, 0xA);

as suggested in the Video for Linux User Guide yet, but not sure what other values to try…

NOTE: We saw similar issues (syncpt error with no error bits marked in register) during the original camera bringup, and the “solution” at that point was to disable some of the error checking done by the VI.

Thanks!

I’d like to suggest you to scope the CSI lanes to figure out if the camera is streaming data to tegra.

Hi there. We can confirm that the Camera is streaming data to the tegra.

It’s more like something is broken between tegra and your camera board.
As you said, camera was streaming data, but probably tegra didn’t receive anything(all the error registers are zero).
Additional, is that possible to switch back your firmware to the older version which you had validated? That will help clarify issues.

The hardware continues to work just fine with the older version of the camera firmware, so it seems very unlikely to be a hardware problem… My guess is that it is more likely to be a timing issue or something along that lines.

We saw similar issues (syncpt error with no error bits marked in register) during the original camera bringup, and the “solution” at that point was to disable some of the error checking done by the VI.

Have you confirmed the clock mode? continuous or discontinuous? Also, the settle time can be ranged from 0 to 0xf.
If none of them can help, I would suggest to scope and analysis the MIPI timing from oscilloscope(such as lp11, lp10 and lp00 transition, settle time, signal quality and etc).