What first comes to mind is that there is more than one CSI/VI module, that the first offset is to the start of all modules, that the second offset is to the particular controller. GPIO does this, but GPIO has different notation. So I started writing down addresses to see how they fit together.
Part of the trail of information, here are some related addresses:
System Address Map (both “CSI” and “VI”):
Start 5408:0000 End: 540b:ffff
I see CSI Pixel Stream A, in order:
Offset: 0x20e | Byte Offset: 0x838
Offset: 0x20f | Byte Offset: 0x83c
Offset: 0x210 | Byte Offset: 0x840
Offset: 0x211 | Byte Offset: 0x844
Offset: 0x212 | Byte Offset: 0x848
Offset: 0x213 | Byte Offset: 0x84c
Offset: 0x214 | Byte Offset: 0x850
Offset: 0x215 | Byte Offset: 0x854
Offset: 0x216 | Byte Offset: 0x858
NOTE: 0x54080000 + 0x216 + 0x858 = 0x54080a63
CSI Pixel Stream B, in order:
Offset: 0x21c | Byte Offset: 0x870
NOTE: 0x54080000 + 0x21c = 0x5408021c
If the first offset is one part of data access from base 0x54080000, and then the second offset is added in for a second purpose of any kind (think GPIO mask registers versus regular registers, or even a second mode), then the end of Stream A final register address would overlap the beginning of Stream B register address…this seems unlikely to be implemented.
NOTE: 0x54080000 + 0x216 = 0x54080216
NOTE: 0x54080000 + 0x858 = 0x54080858
NOTE: 0x54080000 + 0x870 = 0x54080870
…adding either first or second offset of Stream A to base remains below Stream B register start regardless of whether Stream B is base address 0x54080000 first offset or second offset.
It seems that the first memory offset and the second byte offset given are separate registers relative to the base 0x5408000. My thought is nVidia is saving document space in these tables, that there are two registers with the same exact bit patterns and purpose, with some variant on how they behave.
I have not read enough to know why nVidia docs do this, I can only speculate the two registers are linked in some way. Perhaps something for CSI uses the first offset and VI uses the second offset…both CSI and VI are listed as the same base offset 0x5408000 in the System Address Map. I just don’t know enough about CSI/VI to make more of a guess.