Error bringup board CHANSEL_NOMATCH

Robotics & Edge Computing Jetson & Embedded Systems Jetson Xavier NX
1

Hello,

We are bringing a new custom board and facing streaming error :

     kworker/2:3-105     [002] ....   339.372889: rtcpu_vinotify_event: tstamp:11240335732 cch:0 vi:0 tag:FS channel:0x00 frame:0 vi_tstamp:359687478112 data:0x0000000000000010
     kworker/2:3-105     [002] ....   339.372890: rtcpu_vinotify_event: tstamp:11240335872 cch:0 vi:0 tag:CHANSEL_NOMATCH channel:0x01 frame:0 vi_tstamp:359687492992 data:0x00000000000003c9
     kworker/2:3-105     [002] ....   339.428902: rtcpu_vinotify_error: tstamp:11240756599 cch:0 vi:0 tag:CHANSEL_NOMATCH channel:0x01 frame:0 vi_tstamp:359704176064 data:0x00000000000003c9
     kworker/2:3-105     [002] ....   339.428907: rtcpu_vinotify_event: tstamp:11241013853 cch:0 vi:0 tag:FE channel:0x00 frame:0 vi_tstamp:359703478944 data:0x0000000000000020

However, the streaming seems ok if I maximize the clocks of the pipeline’s elements :

#!/bin/bash

[ "$UID" != "0" ] && echo 'Root access is required.' && exit 1


max-clock()
{
    local BASE="/sys/kernel/debug/bpmp/debug/clk"
    local name="$1"
    local clock_base="${BASE}/${name}"

    echo $(cat "${clock_base}/max_rate") > "${clock_base}/rate"
    echo 1 > "${clock_base}/mrq_rate_locked"
    
    echo -n "${name} clock rate is:"
    cat "${clock_base}/rate"
}


for clock in vi isp emc nvcsi; do
    max-clock "$clock"
done

Output :

vi clock rate is:460800000
isp clock rate is:576000000
emc clock rate is:1866000000
nvcsi clock rate is:314000000

Do you think that it is relevant to the hardware, especially to the MIPI-CSI2 signals ?

jnx_trace.txt (30.1 KB)

Best Regards,
Khang

2

I re-tested and with the maximization of only nvcsi clock as above, the stream still worked. But without it, the stream was frozen.

4

Hi again,

Digging more deeply and by seeing that /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate already has same value as /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate (which is 314000000) just after a reboot, the following operation made the streaming work :

# echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked

Does it mean that the above command forces the nvcsi clock to be max value (314000000) permanently?

Best regards,
Khang

5

Adjust the pix_clk_hz/serdes_pix_clk_hz in device tree to acquire high clocks for your case.

6

Hi @ShaneCCC,

Thanks for your reply.

I do not use the GMSLx serializer / deserializer so no need to add/adjust serdes_pix_clk_hz. Do you confirm ?

By the way, based on your experience do you think that the pix_clk_hz needs to be higher for communicating with higher clocks ?

The current device-tree configuration is as below :

			mode0 { /* MODE_1920X1080_30FPS */
				mclk_khz = "24000";
				set_mode_delay_ms = "5000";
				num_lanes = "4";
				tegra_sinterface = "serial_a";
				phy_mode = "DPHY";
				discontinuous_clk = "yes";
				dpcm_enable = "false";
				cil_settletime = "0";

				active_w = "1920";
				active_h = "1080";
				mode_type = "yuv";
				pixel_phase = "uyvy";
				pixel_t = "yuv_uyvy16";

				dynamic_pixel_bit_depth = "16";
				csi_pixel_bit_depth = "16";
				readout_orientation = "0";
				line_length = "2200";
				inherent_gain = "1";
				mclk_multiplier = "2";
				pix_clk_hz = "74250000";

				gain_factor = "10";
				min_gain_val = "10";/* 1DB*/
				max_gain_val = "160";/* 16DB*/
				step_gain_val = "1";
				default_gain = "10";
				min_hdr_ratio = "1";
				max_hdr_ratio = "1";
				framerate_factor = "1000000";
				min_framerate = "1816577";/*1.816577 */
				max_framerate = "60000000";/*60fps*/
				step_framerate = "1";
				default_framerate = "60000000";/*60fps*/
				exposure_factor = "1000000";
				min_exp_time = "34";/* us */
				max_exp_time = "550385";/* us */
				step_exp_time = "1";
				default_exp_time = "33334";/* us */
				embedded_metadata_height = "0";
			};

Best Regards,
Khang

7

Yes, don’t need serdes_pix_clk_hz for none GMSLx serializer / deserializer design.

You can increase the pix_clk_hz to try.

8

Hi @ShaneCCC

No need to increase “mclk_multiplier” ? I tested with mclk_multiplier=30 and the result was the same. Please note that this is an FCB camera and it does not need MCLK from the Jetson.

9

Hi @ShaneCCC,

Effectively, increasing the pix_clk_hz to 4x the original value works for this specific board/hardware. I don’t know yet how to explain but we did have a 2-lane MIPI-CSI2 reference configuration working with pix_clk_hz=74250000, then it continued working well on another board with another 4-lane MIPI-CSI2 configuration, but with the board/hardware in question (also with 4-lane MIPI-CSI2 configuration), we have to increase it 4 times.

We also tested the 2x increment but it did not work even though there was image/frame getting updated half of the screen and the other half was green while in the case pix_clk_hz=74250000, there was 2 smaller frames/images filling the half of the screen and frozen (as below) :

1047b4f16924ca7a9335
1047b4f16924ca7a93351920×1440 161 KB

That led me decide to increase to 4x the pix_clk_hz.

10

Does the bit depth are the same?

11

Reference/working 2-lane configuration based on Jetpack-4.6.x

			mode0 { /* VEYE327_MODE_1920X1080_30FPS */
				mclk_khz = "24000";
				num_lanes = "2";
				tegra_sinterface = "serial_b";
				phy_mode = "DPHY";
				//discontinuous_clk = "no";
				discontinuous_clk = "yes";
				dpcm_enable = "false";
				cil_settletime = "0";

				active_w = "1920";
				active_h = "1080";
				pixel_t = "yuv_uyvy16";
				readout_orientation = "0";
				line_length = "2200";
				inherent_gain = "1";
				mclk_multiplier = "2";
				pix_clk_hz = "74250000";

				gain_factor = "16";
				framerate_factor = "1000000";
				exposure_factor = "1000000";
				min_gain_val = "16"; /* 1.00x */
				max_gain_val = "170"; /* 10.66x */
				step_gain_val = "1";
				default_gain = "16"; /* 1.00x */
				min_hdr_ratio = "1";
				max_hdr_ratio = "1";
				min_framerate = "2000000"; /* 2.0 fps */
				max_framerate = "30000000"; /* 30 fps */
				step_framerate = "1";
				default_framerate = "30000000"; /* 30 fps */
				min_exp_time = "13"; /* us */
				max_exp_time = "333333"; /* us */
				step_exp_time = "1";
				default_exp_time = "2495"; /* us */

				embedded_metadata_height = "0";
			};

Working 4-lane configuration on one board based on Jetpack-5.0.2 in which there’s presence of dynamic_pixel_bit_depth and csi_pixel_bit_depth :

mode0 { /* MODE_1920X1080_30FPS */
mclk_khz = “24000”;
set_mode_delay_ms = “5000”;
num_lanes = “4”;
tegra_sinterface = “serial_a”;
phy_mode = “DPHY”;
discontinuous_clk = “yes”;
dpcm_enable = “false”;
cil_settletime = “0”;

			active_w = "1920";
			active_h = "1080";
			mode_type = "yuv";
			pixel_phase = "uyvy";
			pixel_t = "yuv_uyvy16";

			dynamic_pixel_bit_depth = "16";
			csi_pixel_bit_depth = "16";
			readout_orientation = "0";
			line_length = "2200";
			inherent_gain = "1";
			mclk_multiplier = "2";
			pix_clk_hz = "74250000";

			gain_factor = "10";
			min_gain_val = "10";/* 1DB*/
			max_gain_val = "160";/* 16DB*/
			step_gain_val = "1";
			default_gain = "10";
			min_hdr_ratio = "1";
			max_hdr_ratio = "1";
			framerate_factor = "1000000";
			min_framerate = "1816577";/*1.816577 */
			max_framerate = "60000000";/*60fps*/
			step_framerate = "1";
			default_framerate = "60000000";/*60fps*/
			exposure_factor = "1000000";
			min_exp_time = "34";/* us */
			max_exp_time = "550385";/* us */
			step_exp_time = "1";
			default_exp_time = "33334";/* us */
			embedded_metadata_height = "0";
		};

Above configuration did not work with the board/hardware in question if pix_clk_hz had not been increased 4 times.

Best Regards,
Khang

12

Could you check the nvcsi/vi/emc clocks is the same with JP4.x?

Thanks

14

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