I’m working on testing a custom carrier board which uses both SPI buses. The first SPI works as expected and the pinout matches the documentation. However the signals of the second SPI appear to have their order flipped relative to the documentation. The pinout that I find in the documentation, such as section 5.4 of the document “Jetson Nano System-on-Module Data Sheet” (version 0.7), is as follows:
- Pin 104 -> SPI1_MOSI
- Pin 106 -> SPI1_SCK
- Pin 108 -> SPI1_MISO
- Pin 110 -> SPI1_CS0
However when I configure the second SPI and transmit data while capturing the signals with a logic analyzer I see the signals swapped as follows:
- Pin 104 -> SPI1_CS0
- Pin 106 -> SPI1_MISO
- Pin 108 -> SPI1_SCK
- Pin 110 -> SPI1_MOSI
To double check the issue I used a multimeter, needles, and a microscope to trace from the SPI2 pins of the 40 pin header on an Nvidia carrier board to the SODIMM connector pins (crossing one level shifter). I found that they matched the order in the list above and did not match the documentation. The model number of the Nvidia carrier board that I am using is P3450 and the part number(?) is 180-13449-DAAF-A02. The module has a model number of P3448 and a part number of 180-13448-DAAA-A02.
Can anyone confirm this difference between the documented pinout of the SO-DIMM connector and the actual pinout?