# Eth loss packet

**URL:** <https://forums.developer.nvidia.com/t/eth-loss-packet/320096>\
**Category:** Jetson AGX Orin\
**Tags:** ethernet\
**Created:** [January 15, 2025, 9:46am UTC](https://forums.developer.nvidia.com/t/eth-loss-packet/320096 "2025-01-15T09:46:22Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![837535053](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@837535053](https://forums.developer.nvidia.com/u/837535053)\
**Post date:** [January 15, 2025, 9:46am UTC](https://forums.developer.nvidia.com/t/eth-loss-packet/320096/1 "2025-01-15T09:46:22Z")

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Jetson AGX Orin

JetPack 5.1.2

Problem description:

The interruption distribution of the network port is uneven，This may result in a probability of packet loss。  
cat /proc/interrupts:

 ![image](https://global.discourse-cdn.com/nvidia/original/4X/9/0/7/9072c3e26e4957bbf75eec771d7b9d499c40c541.jpeg)

like the image, The number of interrupts on CPU2 is much higher than on other cores. It is also possible that another kernel has a much higher number of interrupts, which is random.  
RPS as follow：

 ![image](https://global.discourse-cdn.com/nvidia/original/4X/4/9/6/4968deb2d3ed1ce61b1927cbbf7b555f393c5dd5.png)

I tried to modify rps\_cpus and rps\_flow\_cnt values, but after completing the modifications, there was no effect.

thanks

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**Author:** ![KevinFFF](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/kevinfff/32/15508_2.png) [@KevinFFF](https://forums.developer.nvidia.com/u/KevinFFF)\
**Post date:** [January 16, 2025, 1:32am UTC](https://forums.developer.nvidia.com/t/eth-loss-packet/320096/4 "2025-01-16T01:32:56Z")

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Hi 837535053,

Are you using the devkit or custom board for AGX Orin?

Is `MSI ******* ` your custom network device since I cannot find it on AGX Orin devkit?

Please refer to [IRQ Balancing - #6 by sumitg](https://forums.developer.nvidia.com/t/irq-balancing/126244/6) to configure the other cores to handle the interrupt.

```auto
$ sudo su
# cd /proc/irq/331
# cat smp_affinity
# cat smp_affinity_list
# echo ff > smp_affinity

```

Please also refer to [R36.3 Patch to re-enable GICv2m for PCIe MSI interrupts and restore I/O performance - Jetson & Embedded Systems / Jetson AGX Orin - NVIDIA Developer Forums](https://forums.developer.nvidia.com/t/r36-3-patch-to-re-enable-gicv2m-for-pcie-msi-interrupts-and-restore-i-o-performance/297495) and check if those patches can help in your case.

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**Author:** ![837535053](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@837535053](https://forums.developer.nvidia.com/u/837535053)\
**Post date:** [January 16, 2025, 7:21am UTC](https://forums.developer.nvidia.com/t/eth-loss-packet/320096/6 "2025-01-16T07:21:06Z")

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HI。

This uses our self-developed motherboard and NVIDIA ORIN module.

I try two method as follow:

1. Automatically balancing interrupts with irqbalance

2. Manually configure interrupt distribution using the method you described  

But neither method works, it feels like only one CPU’s interrupt count accumulates for each interrupt label over a long period of time。

 ![image](https://global.discourse-cdn.com/nvidia/original/4X/1/0/6/10605133f015fac71b2af8f3b4d692b522d9ffa0.jpeg)

thanks

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**Author:** ![delwyn](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@delwyn](https://forums.developer.nvidia.com/u/delwyn)\
**Post date:** [January 16, 2025, 12:58pm UTC](https://forums.developer.nvidia.com/t/eth-loss-packet/320096/7 "2025-01-16T12:58:03Z")

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For modern NICs that support RSS the driver usually allocates one receive queue per CPU core and the interrupt affinity is set to bind each queue to a specific CPU (as in your first image).

Received packets are directed by the NIC hardware to a queue based on a hash of the packet headers. So the distribution of load across the CPUs depends on the number of flows being received and the relative number of packets in each flow.

RPS won’t help unless you have more CPUs than queues, or your NIC doesn’t support RSS.

Looks like you may be trying to receive a lot of data from a single connection - this will all go to a single queue and therefore one CPU core. If that CPU core is 100% busy then not a lot you can do about it other than increase the packet size to reduce CPU overhead, and ensure any hardware offloading features supported by the NIC are enabled.

See [https://www.kernel.org/doc/Documentation/networking/scaling.txt](https://www.kernel.org/doc/Documentation/networking/scaling.txt)

My patch for R36.3 referred to above won’t help as this code is already present in JetPack 5.1.2, but you’d definitely need it if you ever update to JetPack 6. Without the patch the interrupts for all the queues would be handled on CPU #0

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**Author:** ![system](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/system/32/68080_2.png) [@system](https://forums.developer.nvidia.com/u/system)\
**Post date:** [February 26, 2025, 5:06am UTC](https://forums.developer.nvidia.com/t/eth-loss-packet/320096/9 "2025-02-26T05:06:03Z")

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Closed on February 26, 2025, 5:06am UTC

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