Hi,
I’m trying to do a bare metal implementation on Tegra TK1. I see in the TRM that exception vectors start at 6000:f000 but there isn’t a lot more information other than that. At which address should I place my ISR or exception handling code for IRQs and FIQs?
Also, which model of GIC is the Tegra TK1 using?
thanks,
Jason
Hi Jason,
TK1 has two different types of ARM processors:CPUs(Cortex A15) and COP (ARM7 AVP).
A15 has vGIC : ARM Virtual Generic Interrupt Controller (GIC v2) ARMv7_architecture/RD009-GENC-009281-13-0_arm_architecture_vGIC_specification.pdf
ARM7 has LIC
You can implement your SW like this
NV_NAKED void InitVectors(void)
{
ALIGN
CODE32
/* install vectors */
ldr r0, =(0x6000F200 + 0)
ldr r1, =ResetHandler
str r1, [r0]
ldr r0, =(0x6000F200 + 4)
ldr r1, =CrashHandler
str r1, [r0]
ldr r0, =(0x6000F200 + 12)
ldr r1, =CrashHandler
str r1, [r0]
ldr r0, =(0x6000F200 + 16)
ldr r1, =CrashHandler
str r1, [r0]
ldr r0, =(0x6000F200 + 24)
ldr r1, =CrashHandler
str r1, [r0]
ldr r0, =(0x6000F200 + 28)
ldr r1, =CrashHandler
str r1, [r0]
ldr r0, =(0x6000F200 + 8)
ldr r1, =SwiHandler
str r1, [r0]
/* enable the evt */
ldr r0, =(1 << 4);
ldr r1, =(0x6000C000)
ldr r2, [r1]
orr r2, r0
str r2, [r1]
bx lr
}