Exception Loading Image After "Reboot"

wilkinsw · June 11, 2024, 11:31pm

I’m attempting to load a customized L4T 35.4.1 Image on an AGX Xavier devkit and I have it set as the default extlinux.conf target.

On a POR or hitting the reset button the Image loads correctly. However, if I run the “reboot” command and observe the debug port the following exception is thrown. Is the below log enough to figure out what might be going on?

Press 0-2 to boot selection within 3.0 seconds.
Press any other key to boot default (Option: 2)
��ERROR:   MPIDR 0x80000000: exception reason=0 syndrome=0xbe000000
ERROR:   **************************************
ERROR:   RAS Error in L2, ERRSELR_EL1=0x200:
ERROR:          Status = 0xfc00640d
ERROR:          IERR = SCF to L2 Decode Error Read: 0x64
ERROR:   SERR = Illegal address (software fault): 0xd
ERROR:          Overflow (there may be more errors) - Uncorrectable
ERROR:          Uncorrectable (this is fatal)
ERROR:          MISC0 = 0x200000000100000
ERROR:          MISC1 = 0x805c0000000
ERROR:          ADDR = 0x8000000000000000
ERROR:   **************************************
ERROR:   **************************************
ERROR:   RAS Error in SCF_IOB, ERRSELR_EL1=0x401:
ERROR:          Status = 0xf4009104
ERROR:          IERR = EVP Interface Error: 0x91
ERROR:   SERR = AssertionUnhandled Exception in EL3.
x30            = 0x000000004000f184
x0             = 0x0000000000000020
x1             = 0x000000000c198000
x2             = 0x0000000080000000
x3             = 0x00000000e4642266
x4             = 0x0000000000000000
x5             = 0x0000000000000039
x6             = 0x0000000000000009
x7             = 0x0000000000000000
x8             = 0x0000000000000008
x9             = 0x0000000000000000
x10            = 0x000000000000073d
x11            = 0x0000000060229efe
x12            = 0x000000001ef54dc1
x13            = 0x0000000000000000
x14            = 0x0000000068ac9a75
x15            = 0x000000001a2462c6
x16            = 0x000000004a4e23f8
x17            = 0x000000003f0a35fa
x18            = 0xffffaeb0e5c72c00
x19            = 0x000000004001c960
x20            = 0x00000000ffffff80
x21            = 0x0000000000000020
x22            = 0x00000000400167c0
x23            = 0x0000000040016b00
x24            = 0x0000000040016b00
x25            = 0x0000000000000000
x26            = 0x0000000040010c24
x27            = 0x00000008590d4f18
x28            = 0x00000000ffffffd0
x29            = 0x0000000040016980
scr_el3        = 0x000000000000073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000000
tcr_el3        = 0x0000000080823518
daif           = 0x00000000000003c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x00000000800002cc
elr_el3        = 0x0000000040000ef4
ttbr0_el3      = 0x000000004001dd81
esr_el3        = 0x00000000be000000
far_el3        = 0x0000000000000000
spsr_el1       = 0x0000000000000000
elr_el1        = 0x0000000000000000
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000030d00800
actlr_el1      = 0x0000000000000001
cpacr_el1      = 0x0000000000300000
csselr_el1     = 0x0000000000000004
sp_el1         = 0x0000000000000000
esr_el1        = 0x0000000000000000
ttbr0_el1      = 0x0000000000000000
ttbr1_el1      = 0x0000000000000000
mair_el1       = 0x0000000000000000
amair_el1      = 0x0000000000000000
tcr_el1        = 0x0000000000000000
tpidr_el1      = 0x0000000000000000
tpidr_el0      = 0x0000000100000000
tpidrro_el0    = 0x0000000000000000
par_el1        = 0xff000000a096ab00
mpidr_el1      = 0x0000000080000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0x0000000000000000
cntp_ctl_el0   = 0x0000000000000000
cntp_cval_el0  = 0x000000001b2fed9e
cntv_ctl_el0   = 0x0000000000000000
cntv_cval_el0  = 0x0000000000000000
cntkctl_el1    = 0x0000000000000000
sp_el0         = 0x0000000040016980
isr_el1        = 0x0000000000000000
dacr32_el2     = 0x0000000000000000
ifsr32_el2     = 0x0000000000000000
actlr_el1      = 0x0000000000000001
gicc_hppir     = 0x00000000000003ff
gicc_ahppir    = 0x00000000000003ff
gicc_ctlr      = 0x0000000000000069
gicd_ispendr regs (Offsets 0x200 - 0x278)
 Offset:                        value
0000000000000200:               0x0000000000000000
0000000000000204:               0x0000000000000000
0000000000000208:               0x0000000000000000
000000000000020c:               0x0000000000000000
0000000000000210:               0x0000000000000000
0000000000000214:               0x0000000000000000
0000000000000218:               0x0000000000000000
000000000000021c:               0x0000000000000000
0000000000000220:               0x0000000000000000
0000000000000224:               0x0000000000000000
0000000000000228:               0x0000000000000000
000000000000022c:               0x0000000000000000
0000000000000230:               0x0000000000000000
0000000000000234:               0x0000000000000000
0000000000000238:               0x0000000000000000
000000000000023c:               0x0000000000000000
0000000000000240:               0x0000000000000000
0000000000000244:               0x0000000000000000
0000000000000248:               0x0000000000000000
000000000000024c:               0x0000000000000000
0000000000000250:               0x0000000000000000
0000000000000254:               0x0000000000000000
0000000000000258:               0x0000000000000000
000000000000025c:               0x0000000000000000
0000000000000260:               0x0000000000000000
0000000000000264:               0x0000000000000000
0000000000000268:               0x0000000000000000
000000000000026c:               0x0000000000000000
0000000000000270:               0x0000000000000000
0000000000000274:               0x0000000000000000
0000000000000278:               0x0000000000000000
000000000000027c:               0x0000000000000000

wilkinsw · June 12, 2024, 1:06am

I should mention that the default image always works. It’s something about this built one - but I don’t know how to troubleshoot this sort of exception

kayccc · June 19, 2024, 6:04am

Sorry for the late response.
Is this still an issue to support? Any result can be shared?

wilkinsw · June 19, 2024, 5:06pm

Note: this Image works perfectly on an Orin NX 8GB on an Aetina AIB-MN32 carrier board.

I have tried the Image on two different AGX Xavier devkits and the problem shows up on both. The Xavier’s were previously fully flashed with a different Image based on L4T 35.4.1. The new Image is being dropped into /boot/Image and the extlinux updated appropriately which has always worked before and works on the Orin.

The Xaver’s DTB is the same with both the working and not working Image. The boot exception seems to occur on either a cli “reboot” command or a power-on-reset. However every time I’ve pressed the physical reset button on the Xavier Devkit the Image boots without issue.

Is there a difference in the boot process between a POR and the reset button being pressed?

We have applied patches for qcserial (Sierra LTE modem drivers), the ADAU1761 audio codec, and Nvidia’s IMX185 camera drivers. We also change the MTTCAN driver to built-in. I’m happy to provide those patches or the .config in question.

Our defconfig was generated a while ago and the built .config has the following diff from one generated from tegra_defconfig

$ ../sources/kernel/kernel-5.10/scripts/diffconfig .config ../.config.dax 
-DMIID y
-DMI_SYSFS y
 BMC150_MAGN_I2C n -> m
 BMC150_MAGN_SPI n -> m
 CAN m -> y
 CAN_BCM m -> y
 CAN_DEV m -> y
 CAN_RAW m -> y
 DMI y -> n
 DRM_RCAR_LVDS m -> n
 MTTCAN m -> y
 NF_CONNTRACK_PROCFS y -> n
 OF_OVERLAY y -> n
 PPS_CLIENT_KTIMER n -> y
 PPS_CLIENT_LDISC n -> y
 PPS_DEBUG y -> n
 RANDOM_TRUST_BOOTLOADER n -> y
 RANDOM_TRUST_CPU n -> y
 SND_SOC_ADAU1761_I2C n -> m
 SND_SOC_TEGRA_ADAU1361 n -> m
 SND_SOC_TEGRA_MAX98090 n -> m
 USB_NET_QMI_WWAN n -> m
 USB_SERIAL_QUALCOMM n -> m
+BMC150_MAGN m
+SND_SOC_ADAU1761 m
+SND_SOC_ADAU17X1 m
+SND_SOC_ADAU_UTILS m
+SND_SOC_MAX98090 m
+SND_SOC_SIGMADSP m
+SND_SOC_SIGMADSP_REGMAP m

I will re-build the Image off of tegra_defconfig and see if that fixes the problem.

wilkinsw · June 19, 2024, 9:52pm

I rebuilt our defconfig from tegra_defconfig and the problem went away! Our previous defconfig was built on a different Kernel version so it had some vestigial symbols.

The new diff only contains symbols I added myself.

 CAN m -> y
 CAN_DEV m -> y
 MTTCAN m -> y
 SND_SOC_ADAU1761_I2C n -> m
 USB_NET_QMI_WWAN n -> m
 USB_SERIAL_QUALCOMM n -> m
+SND_SOC_ADAU1761 m
+SND_SOC_ADAU17X1 m
+SND_SOC_ADAU_UTILS m
+SND_SOC_SIGMADSP m
+SND_SOC_SIGMADSP_REGMAP m

system · July 17, 2024, 2:57am

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.

Topic		Replies	Views
How to Sign and Encrypt Kernel image to avoid repeat restart in Jetson AGX Xavier? Jetson AGX Xavier kernel	18	622	June 28, 2023
After update custom Image ,xavier can't boot Jetson AGX Xavier boot	3	925	October 18, 2021
Very slow boot time from SD Card (kernel and initrd load) Jetson Xavier NX boot	10	689	October 18, 2021
AGX Xavier - Boot Hangs - what does this error mean? Jetson AGX Xavier boot , reflash	17	56	November 8, 2024
Kernel driver cannot be updated Jetson AGX Xavier reflash , board-design	28	2622	October 18, 2021
Re-flash the device tree jetson agx xavier Jetson AGX Xavier boot , device-tree	2	1050	December 22, 2021
Unable to update kernel image with nv_update_engine Jetson AGX Xavier kernel	7	1006	October 18, 2021
Enter OEM interface after reboot Jetson AGX Orin reboot	59	1810	December 28, 2022
Modify sensor_common.c Jetson AGX Orin camera	4	24	July 30, 2024
Xavier AGX reboots sometimes after camera frame capturing error Jetson AGX Xavier camera	17	1617	October 18, 2021

Exception Loading Image After "Reboot"

Related topics