I was reading a paper on the existence of minimum energy point for CPU. That is, there exists a frequency point where the energy consumption of the CPU is minimal.
I did some power measurements (total platform power which includes everything) using a bit reverse benchmark (ran the same benchmark 512 times in a loop). The number of elements in the array is fixed 65536 (2^16). I did not want the impact of memory access and hence limited it to 65536 array elements. The benchmark is run on only 1 core (using taskset), the frequency is varied and power measurements are taken and energy consumption calculated. I have disabled the window manager and the peripherals. Running the latest Jetpack.
My energy profile looks like it does not show the minimum energy point. My question is what is your general opinion on the existence of the minimum energy point? and on TX1? There exists such a minimum but my experiment setup is skewed? How much it is related to the CPU architecture? and other insights?
The paper I read and the graph I obtained can be found in the link below.
The minimum energy state for the CPU is when it is disabled and rail gated (for example in SC7 standby state).
If you’re looking for the best CPU perf/W point, this is typically at the highest freq for the lowest VCPU voltage supported.
If you’re looking for the best AP perf/W (i.e. entire chip), it is typically with all unused units in power gated state and SDRAM at the highest freq supported at the lowest VSOC voltage.
Thanks for the reply.
Can a single frequency point have multiple supported operating voltages? I mean, if a CPU/core is running at say 1730 MHz (highest frequency of TX1), can it have multiple operating voltages (VCPU’s supported?). What unit makes this decision at run-time and under what conditions?
Yes, multiple voltages for one single frequency is possible. There is a dedicated scheme part to calculate whole system loading and so adjust frequency and power voltage. In some cases different voltages could be with same frequency. This scheme is validated and not exposed to customer, just know this and please do not intend to modify.
For example in my experiment above, I fixed the frequency for a core using cpufreq-set (governor: userspace) like below. Do you mean to say that even when you pin the frequency on a core there would be multiple voltages it would be operating on? And the voltage can vary during the execution of the program even though you have fixed the frequency?
cpufreq-set -g userspace;
cpufreq-set -c $CORE -f $FREQ;
There is a dedicated scheme part to calculate whole system loading and so adjust frequency and power voltage. In some cases different voltages could be with same frequency. This scheme is validated and not exposed to customer, just know this and please do not intend to modify.
I understand (from a previous comment made by @chijen) that the mechanism for the voltage scaling is based on intended CPU frequency and coefficient table. The hardware (closed-loop dvfs) will come up with an appropriate voltage and go through i2c to program PMIC power rails. This seems to be described in tegra21_dvfs.c.
When you say that “this scheme is validated and not exposed to customer” do you refer to the hardware (closed-loop dvfs) part? More specifically what is not exposed to the customer?
Yes, it is dvfs. For a given CLK, there is a corresponding minimum operating VDD. If the VDD is lower, there will be functional failures. If the VDD is higher, the circuits should still operate correctly, but will consume higher power. These adjustment limits and scheme are fixed and should not be changed, that’s what i mean not exposed.
I am working on DVFS, I would like to know how you exactly achieved DVFS on Jetson TX1 ?
What are the steps to be carried out to achieve DVFS on Jetson TX1 , whether linux was ported on board and you tried to set the particular voltage corresponding to a frequency ?
Or what are the ways or steps to achieve DVFS ?
I want to achieve DVFS on this board with different algorithm stack in C++ and Python , each algorithm sets a particular voltage level.
Please do let me know whether this can be achieved on Jetson TX1 platform.
Thanks and Regards