Earlier question asks this; to extend on it. Is there an acceptable means for measuring current and voltage through VDD_CVM that can be captured externally. I have an automated external power measuring setup with a power analyser and only need to find/create a break after Q50 on the carrier board / anywhere along VDD_CVM to observe power consumption and fast transients while the Orin Nano module is working on an algorithm we are devloping. Hoping for just the module to be monitored and not the peripherals.
These transients are easier captured on my power analyser as tegrastats cannot meet the need.
Are there NVIDA approved carrier boards with better access/jumpers/0ohm resistors suitable for this? would we need to develop our own carrier for these tests or are there other recommendations for this task.
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I could not find clear support for that in the provided Jetson Orin Nano documentation. The context does not provide information on measuring current draw or power consumption of the Jetson Orin Nano on a carrier board, nor does it mention approved carrier boards with features suitable for such measurements. The provided documentation focuses on the Jetson Orin Nano’s capabilities, applications, and software aspects, but does not cover hardware-level measurements or modifications to the carrier board. If you are looking for a way to measure the power consumption of the Jetson Orin Nano module specifically, without including peripherals, you may need to consult additional resources or contact NVIDIA support directly for more detailed guidance.
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Does tegrastats provide additional information that you don’t need and you specifically need to focus on a subset of its output?
The Orin Nano module integrates a TI INA3221 monitor and there are sysfs nodes that can be directly accessed to check current and voltage. Channel 1 of the INA3221 monitors the VDD_IN for total module power.
It’s more to access that power rails without further load on the processor for parity with other experiments (I know its very low overhead) and also the INA3221 capture rate is quite slow compared to the capture rate of our preconfigured external power monitor and some of the transients we are expecting to observe. However; it does appear that for this work to be done we may need to design a carrier that exposes a break in series on VDD_CVM after the MOSFET at Q50. Track cuts and reworks will be too complex an endeavour otherwise. I saw a test point that can monitor VDD_CVM so voltage can be observed but unless mistaken I cannot find any 0ohm or places to easily place a shunt or create a gap on that rail.
The boards in our test environment will be unable to communicate directly with observation equipment during runs but our external test equipment will be interfaced and trigger tests via GPIO that said, we will adjust for this case.
Thank you however as the information provided has been useful, it provided much needed clarity and info I had overlooked.
A custom carrier adding the sense resistor after Q50 and proper routing/connectors to your external monitor sounds like your best option. The carrier board layout is provided in the Jetson Orin Nano Developer Kit Carrier Board Reference Design Files package but you are correct that cutting traces to rework a sense resistor is complex.