Extra bit in SPI slave transfer

I have the Nano developer kit configured for SPI slave on the spi@7000d400 node. I receive data from the master correctly, but data transferred to the master has an extra bit at the start so all data from the slave is right-shifted by 1 bit.

The SPI slave is configured with the correct clock polarity and phase and the clock rate is low at 2MHz. Any recommendations for device tree settings (or missing settings) that could cause this behavior?

What’s your BSP version?

cat /etc/nv_tegra_release

R32 (release), REVISION: 4.4, GCID: 23942405, BOARD: t210ref, EABI: aarch64, DATE Fri Oct 16 19:44:43 UTC 2020

Could you add nvidia,lsbyte-first like below to device tree to try.

spi@0 {
compatible = "tegra-spidev";
reg = <0>;
spi-max-frequency = <81000000>;
controller-data {

For enabling the dump registers you need to run the below commands on the target after the boot this would enable dynamic debug prints

echo -n "file drivers/spi/spi-tegra124-slave.c +p" > /sys/kernel/debug/dynamic_debug/control
echo -n "file drivers/spi/spi-tegra114.c +p" > /sys/kernel/debug/dynamic_debug/control
echo 8 > /proc/sys/kernel/printk

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