Extra "hidden" RT processors on NX


I once heard besides the 6 CPU arm cores and the GPU cores there are more processors, can someone confirm this ? and how do I program them ?


You are probably refering to the DLAs (deep learning accelerator)?

see http://nvdla.org for more details

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There are a couple of specialty processors normally reserved which are Cortex-R5 processors. Not sure what the procedure is to access those (at the cost of losing their assigned function).

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Can you like me to any document about them ? thanks !

is Programmable Vision Accelerator the same thing?

Hi @wenbin.leong, please refer to the Jetson Sensor Processing Engine (SPE) Developer Guide and example sources:

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The Vision Accelerator is different than the Cortex-R5 SPE and the DLA’s. You can use the Xavier’s Vision Accelerator through the Vision Programming Interface (VPI):

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Does SPE shared memory with NX memory? how can I share memory with my app ? And does the GPIO has a GPIO Pin out ?

Hello, wenbin:

  1. SPE can share memory with CCPLEX. The IVC is implemented through shared memory. You can check the corresponding code (ivc-channels.c) for details.
    Note that you have also check the driver in CCPLEX (Linux) side.
  2. SPE can access GPIO pins in AON cluster, and there’s an example for GPIO in/out app. Refer to gpio-app.c for details.