Hi @ShaneCCC.
I re-did the test with the rce firmware mentioned here : Camera failed with log:VIFALC_TDSTATE on Jetpack5.0.2 - #4 by JerryChang :
[ 163.622618] adv7280: adv7180_s_stream( enable=1 )
[ 163.646224] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 2, flags: 0, err_data 131072
[ 163.673106] [RCE] VM0 deactivating.VM0 activating.NVCSILP clock rate = 204000000 Hz.
[ 163.673129] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=4, csi=4)
[ 163.673142] [RCE] MIPI clock = 102000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[ 163.673151] [RCE] ===== NVCSI Stream Configuration =====
[ 163.673160] [RCE] stream_id: PP 4, csi_port: PORT E
[ 163.673169] [RCE] Brick: PHY 2, Mode: D-PHY
[ 163.673178] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 1
[ 163.673187] [RCE] Clock information:
[ 163.673196] [RCE] MIPI clock rate: 102.00 MHz
[ 163.673204] [RCE] T_HS settle: 0, T_CLK settle: 0
[ 163.673213] [RCE] ======================================
[ 163.673222] [RCE] tegra_nvcsi_stream_open(vm0, stream=4, csi=4)
[ 163.673231] [RCE] nvcsi_calc_ths_settle ths_settle 25
[ 163.673240] [RCE] nvcsi_calc_ths_settle ths_settle 25
[ 163.673249] [RCE] nvcsi_calc_tclk_settle tclk_settle 33
[ 163.678901] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 2, flags: 0, err_data 131072
[ 163.692651] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 131072
[ 163.709547] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 131072
Full dmesg and trace are attached.
dmesg.txt (94.8 KB)
adv7280m.trace2 (1.9 MB)
In the following video, I was able to capture from the beginning and nearly the end of the vokoscreen video but this rarely happened, and then failed multiple of times (same as Jetpak-4.6.x) : jp502-adv7280m-unstable.mkv - Google Drive
Regards,
K.