command:
/usr/src/tensorrt/bin/trtexec --onnx=stereo.onnx --workspace=8000 --saveEngine=depth.trt --fp16
part of error log:
[06/21/2023-16:14:40] [V] [TRT] Conv_223 + PWN(Clip_226) Set Tactic Name: sm80_xmma_fprop_implicit_gemm_indexed_f32f32_f32f32_f32_nchwkcrs_nchw_tilesize128x32x8_stage3_warpsize2x2x1_g1_ffma_aligna4_alignc4 Tact\
ic: 0xa9366041633a5135
[06/21/2023-16:14:40] [V] [TRT] Tactic: 0xa9366041633a5135 Time: 0.324192
[06/21/2023-16:14:40] [V] [TRT] Conv_223 + PWN(Clip_226) Set Tactic Name: sm80_xmma_fprop_implicit_gemm_f32f32_f32f32_f32_nchwkcrs_nchw_tilesize64x64x8_stage3_warpsize1x4x1_g1_ffma_t1r3s3_aligna4_alignc4 Tactic\
: 0x4727434768e46395
[06/21/2023-16:14:40] [V] [TRT] Tactic: 0x4727434768e46395 Time: 0.331346
[06/21/2023-16:14:40] [V] [TRT] Conv_223 + PWN(Clip_226) Set Tactic Name: sm80_xmma_fprop_implicit_gemm_f32f32_f32f32_f32_nchwkcrs_nchw_tilesize128x64x8_stage3_warpsize2x2x1_g1_ffma_aligna4_alignc4 Tactic: 0x12\
dbf7d94ee3696d
[06/21/2023-16:14:40] [V] [TRT] Tactic: 0x12dbf7d94ee3696d Time: 0.322405
[06/21/2023-16:14:40] [V] [TRT] Fastest Tactic: 0xa8609adc4e0ceb90 Time: 0.224914
[06/21/2023-16:14:40] [V] [TRT] --------------- Timing Runner: Conv_223 + PWN(Clip_226) (CaskFlattenConvolution)
[06/21/2023-16:14:40] [V] [TRT] CaskFlattenConvolution has no valid tactics for this config, skipping
[06/21/2023-16:14:40] [V] [TRT] >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: 0xa8609adc4e0ceb90
[06/21/2023-16:14:40] [V] [TRT] *************** Autotuning format combination: Float(2621440,1,16384,64) long-strided -> Float(327680,1,4096,32) ***************
[06/21/2023-16:14:41] [V] [TRT] --------------- Timing Runner: Conv_223 + PWN(Clip_226) (CaskConvolution)
[06/21/2023-16:14:41] [V] [TRT] Conv_223 + PWN(Clip_226) Set Tactic Name: ampere_scudnn_128x128_relu_exp_medium_nhwc_tn_v1 Tactic: 0xd9031472c05adf51
[06/21/2023-16:14:41] [V] [TRT] Tactic: 0xd9031472c05adf51 Time: 0.519849
[06/21/2023-16:14:41] [V] [TRT] Conv_223 + PWN(Clip_226) Set Tactic Name: ampere_scudnn_128x64_sliced1x2_ldg4_relu_exp_small_nhwc_tn_v1 Tactic: 0x27b316f52c109002
[06/21/2023-16:14:41] [E] Error[1]: [resizingAllocator.cpp::deallocate::105] Error Code 1: Cuda Runtime (misaligned address)
[06/21/2023-16:14:41] [E] Error[1]: [resizingAllocator.cpp::deallocate::105] Error Code 1: Cuda Runtime (misaligned address)
[06/21/2023-16:14:41] [E] Error[1]: [resizingAllocator.cpp::deallocate::105] Error Code 1: Cuda Runtime (misaligned address)
[06/21/2023-16:14:41] [W] [TRT] Skipping tactic 0x27b316f52c109002 due to exception misaligned address
[06/21/2023-16:14:41] [W] [TRT] Skipping tactic 0x412c44dfeaf9161d due to exception misaligned address
[06/21/2023-16:14:41] [W] [TRT] Skipping tactic 0x3e2b881168d9689d due to exception misaligned address
[06/21/2023-16:14:41] [W] [TRT] Skipping tactic 0xbdfdef6b84f7ccc9 due to exception misaligned address
[06/21/2023-16:14:41] [W] [TRT] Skipping tactic 0xf90060ce8193b811 due to exception misaligned address